Si5348 have 3 output enable pins, i.e. OE0b, OE1b and OE2b. Those output enable pins can be mapped to control any of the outputs (OUTx) through the configuration steps below:

Step 1: Set 0x0022h[0] = 0 to enable using OExb pins to control the outputs. 

Step 2: Set the mask registers below to map the outputs to OExb pins.

OExb mask registers (above) are used to configure the outputs to be under control by OExb pins (logic 1) or not (logic 0), respectively. Note that the same bit of three OExb mask registers should not be set as 0 at the same time otherwise the corresponding output will be disabled no matter OExb pins inputs.

This is following the example mappings from the table above:

Example Out 0, Out 1, Out 2 controlled by OE0b pin.

Write 0x0023h = 0x38h

Write 0x0024h = 0x00h

Example Out3, Out4 and Out5 controlled by OE1b pin.

Write 0x0025h = 0x80h

Write 0x0026h = 0x03h

Example Out 6 controlled by OE2b pin.

Write 0x0027h = 0x00h

Write 0x0028h = 0x08h

The clock generator devices like Si5340/41/91 as well as the jitter attenuator devices like Si5345/95 are both designed to provide low jitter output clocks. But a major difference is that the jitter attenuators, as the name suggests, will attenuate the noise/jitter at the input while for the clock generators, the noise at the input passes through to the output and contributes to the output jitter value.

Therefore, in case of the clock generator devices, the total RMS jitter at the output will tremendously depend on the jitter of the input source and also on the input frequency. In order to get the best jitter performance, it is recommended to use an input frequency between 48MHz to 54MHz at the XAXB pins of these devices and also to avoid using low frequencies like 20MHz or 25MHz at the input. Lower input frequencies cause an increase in noise at the clock output which is seen as increased RMS jitter.

The above applies to both the XAXB pins and the clock inputs pins for the clock generators.

Also, the signal generator or the oscillator used at the input should have minimum possible jitter. The Rohde & Schwarz SMA 100 signal generator is one of the very low jitter signal generators available

Now in case of the jitter attenuating clocks, any allowed input frequency and any signal generator can be used to produce the input signal and it will not have any effect on the output clock jitter.

Frequency accuracy is an important parameter when selecting a reference clock for any application. In general frequency accuracy is the difference in the measured value of the crystal/XO/TCXO/OCXO frequencies from the ideal expected value.

Following factors contribute to the accuracy measurement:

1. Initial accuracy: It is the deviation of the clock frequency from the ideal value when measured at room temperature. Any crystal/XO/TCXO/OCXO datasheets specify this value as Initial Tolerance.

2. Accuracy over temperature: This is the deviation of the clock frequency from the reference frequency (Ref Freq).

Frequency of a crystal/XO/TCXO/OCXO is measured after placing the device in a temperature-controlled chamber and then varying the temperature from -40°C to 85°C. Then the frequency accuracy at a particular temperature is calculated in ppm as follows:

Facc = Frequency accuracy at particular temperature

Ft = Frequency at particular temperature

Fref = Frequency at 25°C

This Ref freq can be calculated using any of the following two techniques (this is usually specified in the datasheet for the device):

1. The frequency measured at 25°C (room temperature) is taken as reference
2. Reference frequency is the average of frequency measured at the extreme temperatures. For example:

DCO mode allows the user to dynamically change an output clock frequency in any existing device or OPN if required. The output frequency can be modifying by changing the N divider value which is assigned to the particular clock output. However manually writing to the N dividers is not a recommended way to use the DCO mode. There are certain factors which need to be considered.

The N divider which is associated with the DCO enabled output should be in fractional mode. If the N divider is integer in the original project file, then it needs to be changed to operate in the fractional mode. The register PIBYP[4:0] enables to change the N divider mode. Each bit in this register is assigned to one N divider. If N0 needs to be in fractional mode, write 0 to PIBYP[0]. Note that a soft reset should be performed after changing the above mentioned register.

The next step involves calculating the frequency step word and then also the corresponding values for either the N divider numerator or the N divider denominator. All these calculations are explained in detail in the following application note:

https://www.silabs.com/documents/public/application-notes/AN959.pdf

In order to avoid all these complications, the best and easiest way to implement DCO mode is using Clock Builder Pro DCO mode tool. It will perform all the calculations and determine the required register values.

Many applications require output frequencies that are not integers and are represented using very specific decimal values. Clock generators and Jitter attenuators (Si534x/9x) devices are capable of generating all types of frequency outputs. When a required input-output configuration file is generated, Clock Builder Pro calculates the values of the M, N and P dividers according to the input-output frequencies.

The M and N dividers are in the form of a multiplication ratio. Calculating these values is very tricky when the output frequencies are not integers. In order to get the correct multiplication ratio, it is important to express the frequency values in an exact manner. This means that the decimal frequencies should not be rounded. They should be expressed in terms of fractions. Many times, the output frequency is in terms of repeating decimals. If these are rounded, then there is possibility of getting incorrect divider values.

For example, if a 33.3333… MHz output is required, it should be expressed as 100/3 MHz and not rounded to 33.333 MHz. The following table will show the difference in the M and N divider register values between 33.333 MHz and 100/3 MHz output frequency.

The left side shows register values when the output frequency is 33.333 MHz and the right side shows when it’s 100/3 MHz. As seen the M divider and N divider values are different and in order to get a perfect multiplication ratio, decimal frequencies should be expressed as fractions.

With limitation of Keysight E5052B, it can't measure phase noise when the carrier frequency less than 250MHz. 

If one application need to see the phase noise at 100MHz while the carrier frequency is less than 250MHz, then they may need below two methods:

1. Test the frequency directly, and simply use the phase noise number at 40MHz or 20MHz, usually the far end to 100MHz phase noise trace is the extensions.

2. Double or quadruple the carrier frequency to make sure the carrier frequency larger than 250MHz and now you can the span of E5052B to 100MHz,  and then plus 6 and 12 to get the actual carrier frequency phase noise. (Note: phase noise decreased by 6db every twice, it comes from a simplified function 20lg(f2/f1) ).

There is some tables to show the I2C data protocol in datasheet. Here is some figures to illustrate the protocol clearly.

1. Block Read 

2. Block Write

3. Byte Read

4.Byte Write

Please be noted that Si53152/4/6/9 all need a valid input clock in order for the I2C interface to work.

CBPro implements the DCO function on a Si5395/94/92/45/44/42 by changing the numerator (Nx_NUM) as this gives a higher resolution than changing the N divider denominator (Nx_DEN). However the DCO function can be implemented by changing the Nx_DEN value and this KB article describes how to do this. Note that when changing the Nx_DEN value instead of the Nx_NUM value the minimum step size will increase by approximately the Nx divider value.  This is because the Nx_NUM register is 44 bits and the Nx_DEN register is 32 bits. Changing the Nx_NUM term causes an extremely small non-linearity, which will not be a problem except for very rare applications. Changing the Nx_DEN term does not cause any non-linearity.    

The DCO function of Si5395/94/92/45/44/42 devices is implemented by changing the Nx_DEN value in one of two ways:

1. Using FINC/FDEC by writing these register bits or pulsing the FINC/FDEC pins.
2. Directly writing to the Nx_DEN bits.

Here is the procedure to implement a DCO function by changing the Nx_DEN term:

1. Create a starting frequency plan using ClockBuilder Pro.

1. Set the DCO range in CBPro.
2. Set the desired DCO step size in CBPro
   1. CBPro will compute Nx_FSTEPW based upon changing the Nx_NUM value but this Nx_FSTEPW will have to be manually re-calculated.
   2. The min step size in Hz when using Nx_DEN is by definition Fvco/(Nx_NUM*R). Make sure that your desired step size is not smaller than this.
3. Note the register values of Nx_DEN and Nx_NUM that are connected to the output clocks that you want to control via DCO. You can do this by looking at the Design Report that comes up when you click on “Frequency Plan Valid” at the bottom left of a CBPro page.

2. Make sure that the denominators that you are going to change are enabled for FINC/FDEC control because CBPro by default will change the Nx_NUM.

1. N_FSW_DEN[4:0] = 0x033A[4:0] = N_FSW_DEN[N4, N3, N2, N1, N0]. Set the appropriate bit(s) = 1 to enable modifying the Nx_DEN when using FINC/FDEC.

3. Compute the Nx_DEN_delta for your required frequency step size.

1. Nx_DEN_delta = floor(Nx_DEN × Fout_step_ppm × 1e-6).
2. If Nx_DEN_delta is < 1 then the step size is too small to implement.

4. Calculate the actual step size in ppm from Nx_DEN_delta as follows:

1. Actual step size in ppm = (Nx_DEN_delta / Nx_DEN) × 1e6.

5. If you are going to use the FINC/FDEC pins or register bits to change the output frequency then:

1. Write the respective bits of N_FSW_DEN[4:0] = 1 to enable modifying the denominators via FINC/FDEC control.  N_FSW_DEN[4:0] = 0x033A[4:0] = 0x033A[N4, N3, N2, N1, N0].
2. Each assertion of FINC or FDEC will now change the output frequency by Actual step size in ppm.

6. If you are going to write the Nx_DEN value directly (not use FINC/FDEC) then:

1. Calculate Nx_DEN_new = Nx_DEN_old +- Nx_DEN_delta.
2. Then write Nx_FUPD= 1 to cause this Nx_DEN_new value to become active. i.e. change the Nx divider value that is being used.
3. You can write  Nx_DEN_new (a separate value for each N divider if you like) to multiple N dividers and then write N_FUPD = 1 and then all of the Nx_DEN_new values will be made active and all the other N divider values will not change or glitch.

More information about DCO applications for Si5395/94/92/45/44/42 can be found at:

https://www.silabs.com/documents/login/reference-manuals/si5395-94-92-family.pdf

https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf

https://www.silabs.com/documents/public/application-notes/an858-dco-applications-jitter-attenuators.pdf

The Si5395/94/92/91/45/44/42/41 parts have a maximum output frequency of 1028 MHz. However, there are a few gaps below 1028 MHz which are not valid output frequencies. Why is this the case?

The output clock frequency is equal to the VCO frequency divided down by an output divider. Below 720 MHz, the output divider is able to operate in either fractional or integer mode. Therefore, any output frequency below 720 MHz can be synthesized. Above 720MHz, however, the output divider must be equal to an even integer value, with an exception made for the odd value of Fvco/Fout = 15. The dual constraints of an even integer divide ratio and a limited VCO tuning range lead to a couple of small gaps in the allowed output frequencies. More specifically, the frequencies from 720 MHz --> 733.334 MHz and 800 MHz --> 825 MHz are not valid output frequencies. The figure below shows a conceptual diagram of the valid and non-valid output frequency ranges. The blue areas show the valid output frequency ranges, and the red areas show the non-valid output frequency ranges.

The above definition of the valid and non-valid output frequency ranges holds true only if one unique frequency from the upper frequency range (720 MHz --> 1028 MHz) exists in the frequency plan. This is because selecting an output frequency from the 720 MHz --> 1028 MHz range fixes the VCO frequency. Therefore, selecting two or more unique output frequencies (noting that they both require integer dividers) from the upper range may present competing requirements for the VCO frequency and hence result in a non-synthesizable frequency plan.

A few examples of valid and non-valid frequency plans are listed below:

• FOUT1 = 1028 MHz and FOUT2 = 800 MHz is valid since both FOUT1 and FOUT2 require FVCO = 14.4 GHz.
• FOUT1 = 850 MHz and FOUT2 = 790 MHz is not valid, since FOUT1 requires FVCO = 13.6 GHz and FOUT2 requires FVCO = 14.22 GHz
• FOUT1 = 850 MHz and FOUT2 = 156.25 MHz is valid, since FOUT1 requires FVCO = 13.6 GHz and FOUT2 does not place any constraints on the VCO frequency.