With limitation of Keysight E5052B, it can't measure phase noise when the carrier frequency less than 250MHz.
If one application need to see the phase noise at 100MHz while the carrier frequency is less than 250MHz, then they may need below two methods:
1. Test the frequency directly, and simply use the phase noise number at 40MHz or 20MHz, usually the far end to 100MHz phase noise trace is the extensions.
2. Double or quadruple the carrier frequency to make sure the carrier frequency larger than 250MHz and now you can the span of E5052B to 100MHz, and then plus 6 and 12 to get the actual carrier frequency phase noise. (Note: phase noise decreased by 6db every twice, it comes from a simplified function 20lg(f2/f1) ).
There is some tables to show the I2C data protocol in datasheet. Here is some figures to illustrate the protocol clearly.
1. Block Read
2. Block Write
3. Byte Read
Please be noted that Si53152/4/6/9 all need a valid input clock in order for the I2C interface to work.
CBPro implements the DCO function on a Si5395/94/92/45/44/42 by changing the numerator (Nx_NUM) as this gives a higher resolution than changing the N divider denominator (Nx_DEN). However the DCO function can be implemented by changing the Nx_DEN value and this KB article describes how to do this. Note that when changing the Nx_DEN value instead of the Nx_NUM value the minimum step size will increase by approximately the Nx divider value. This is because the Nx_NUM register is 44 bits and the Nx_DEN register is 32 bits. Changing the Nx_NUM term causes an extremely small non-linearity, which will not be a problem except for very rare applications. Changing the Nx_DEN term does not cause any non-linearity.
The DCO function of Si5395/94/92/45/44/42 devices is implemented by changing the Nx_DEN value in one of two ways:
Here is the procedure to implement a DCO function by changing the Nx_DEN term:
More information about DCO applications for Si5395/94/92/45/44/42 can be found at:
The Si5395/94/92/91/45/44/42/41 parts have a maximum output frequency of 1028 MHz. However, there are a few gaps below 1028 MHz which are not valid output frequencies. Why is this the case?
The output clock frequency is equal to the VCO frequency divided down by an output divider. Below 720 MHz, the output divider is able to operate in either fractional or integer mode. Therefore, any output frequency below 720 MHz can be synthesized. Above 720MHz, however, the output divider must be equal to an even integer value, with an exception made for the odd value of Fvco/Fout = 15. The dual constraints of an even integer divide ratio and a limited VCO tuning range lead to a couple of small gaps in the allowed output frequencies. More specifically, the frequencies from 720 MHz --> 733.334 MHz and 800 MHz --> 825 MHz are not valid output frequencies. The figure below shows a conceptual diagram of the valid and non-valid output frequency ranges. The blue areas show the valid output frequency ranges, and the red areas show the non-valid output frequency ranges.
The above definition of the valid and non-valid output frequency ranges holds true only if one unique frequency from the upper frequency range (720 MHz --> 1028 MHz) exists in the frequency plan. This is because selecting an output frequency from the 720 MHz --> 1028 MHz range fixes the VCO frequency. Therefore, selecting two or more unique output frequencies (noting that they both require integer dividers) from the upper range may present competing requirements for the VCO frequency and hence result in a non-synthesizable frequency plan.
A few examples of valid and non-valid frequency plans are listed below:
People sometimes mix the definitions of Time Interval Error (TIE) jitter and period jitter and easily make a common mistake of calculating TIE jitter but with period jitter formula for a spread spectrum clock (SSC). Let's denote the clock frequency as F, the down spread linear modulation as d, the modulation rate as fm, and then the increase of peak to peak value of period jitter due to spread spectrum is given by:
PJpp = d/((1-d)F);
the increase of peak to peak value of TIE jitter due to spread spectrum is given by:
TIEJpp = d/(8fm).
Take a PCIe SSC as an example: F = 100MHz, d = 0.5% (down spread), fm = 30KHz - 33KHz. It gives a PJpp of 0.05 ns and a TIEJpp of 18.9ns - 20.8ns.
Regarding DDR design, there are some clock such as 33.333333...MHz, 133.333333...MHz and 166.666666...MHz etc. Generally 33.333333MHz, 133.333333MHz and 1666.666666MHz are used to approximate value. This method will introduce more spurs and less accuracy.
Silicon Labs Multisynth technology can support 100MHz/3, 400MHz/3 and 500M/3 configuration to get exact clock with 0ppm. This configuration can reduce spurs as well.
The recommended termination is shown below.
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedance and drive strengths. A series source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance (Rs = Trace Impedance – Zs). For example, the driver impedance Zs is configured to 38 Ohm, and the trace impedance is 50 Ohm. So the Rs is 12 Ohm.
1. If you change output impedance, please change Rs accordingly.
2. Use of the complementary CMOS for one pair OUTx/OUTxb is recommended to help balance the output current surges during transitions. It will reduce the crosstalk noise for adjacent channel.
3. Generally, the lowest impedance for a given supply voltage is preferable, since it will give the fastest edge rates. The faster edge rate means more crosstalk noise to adjacent channel. If the jitter performance of adjacent channel is high priority, the higher impedance should be selected to reduce the noise.
These transients can be removed by the following process
1. Set OUT_PDN_ALL = 1 (0x0145 = 1) before any registers of the new plan are written
2. Just before the post amble is written (after all the other writes), set OUT_PDN_ALL = 0 (0x0145 = 0)
The Si5386/82/81 is internally optimized to output the LTE/CPRI frequencies with the lowest possible phase noise (jitter) using a very low noise external 54 MHz XO. For this reason the 5386 can be expected to have lower output phase noise and spurs than a 5345/95 for LTE/CPRI frequencies.
The factors that affect the Si5345 output phase noise are?
The Si5381/82/86 are intended for high performance wireless applications which require ultra low close-in phase noise and have very tight spur masks. To meet these high demands we recommend the customer use one of the 54 MHz XOs listed in table 2.3 of the recommended crystal oscillator (XO) reference manual https://www.silabs.com/documents/public/reference-manuals/si534x-8x-9x-recommended-crystals-rm.pdf. These XOs have a very low close-in phase noise profiles as well as low jitter.
Although the Si5381/82/86 device itself has many LDOs on-chip and very good PSR, XOs most of the time do not. Any power supply noise on the XO greater than the DSPLL BW will be seen at the output of the Si5381/82/86 device. For this reason it is critical to use a low noise LDO to supply power to these oscillators. An example of an ultra low noise LDO can be seen in the Si5386A-E-EVB schematics https://www.silabs.com/products/timing/clocks/wireless-jitter-attenuators/device.si5386a. Typically we recommend LDOs with less than 10 uVrms noise integrated from 10 Hz to 100 kHz.
It is acceptable to use the same LDO to supply power to the other 3.3V supplies on the SI538x device such as VDDA or VDDOx but it is not recommend to use this LDO to supply power to other ICs in your system.
For the Si5381/82/86 devices a thermal report can be viewed in the CBPro Wizard by clicking on the green temperature widget in the bottom panel, highlighted in yellow below. This tool is intended to help provide confidence for customers designing the Si5381/82/86 into higher temperature environments such as outdoor remote radiohead applications.
The report includes estimates of the typical power consumption and junction temperature (Tj) for an ambient temperature (Ta) that is input by the customer. The default Ta for typical power estimation is 25C.
The customer has the option to specify an airflow condition of 0 m/s, 1 m/s, 2 m/s depending on the airflow in their system. More airflow will result in a lower thermal resistance (ThetaJA) and lower Tj for the same frequency plan.
The power estimator always provides an estimate for the worst case Tj assuming the maximum Ta = 85C as specified in the device datasheet. The worst case condition also assumes supplies at nominal +5% voltage and takes into account increased leakage current possible at the extremes of normal process variations. This estimate is intended to give customers guardband against the maximum specified Tj for these devices which is 125C. At higher Tj than 125C datasheet performance can no longer be guaranteed.
The short answer is no.
The Reference Manuals for the Si534x/7x/8x/9x clock generator and jitter attenuator devices all illustrate single-ended external reference clocks connected by circuitry to the device's XA pin. The XB input pin is then AC-coupled to ground.
The Si5381/82 and Si5386 Rev. E Reference Manuals go further and explicitly state that "Single-ended inputs must be connected to the XA pin with proper termination on the XB pin. Because the signal is single-ended in this case, the XB input is ac-coupled to ground."
The reason why is that there is peak-detection and LOS circuitry present on the XA signal path that is not present on the XB signal path. The XA/XB interface is simply not functionally symmetric with respect to to single-ended reference clocks.
For CMOS output, usually we need to add series resistor at source end to make sure source end impedance matched since the cap load(impedance unmatched at load end), or the signal integrity will be bad. Please check part's datasheet for specific impedance of CMOS output.
Please refer to below diagram for detail information:
What is output skew?
Output skew is a user defined time delay added to each N-divider, which may be useful to adjust the relative phase of the outputs. Output skew can be categorized into dynamic skew and static skew. Static skew is a change in the output phase that is done once at power up or after a reset. Static skew is used if a known absolute time difference is required from the input to the output. Dynamic skew is a change in the output phase that can be done while the part is still running, and no reset is done.
Which products offer what type of output skew?
Within the Si534x/7x/8x/9x product line, the table below shows the availability of static and dynamic skew for the wired and wireless clocks. If applicable, the resolution of the skew is also given in terms of Fvco, where Fvco is the VCO frequency.
Under high device junction temperatures in the Si534x/7x/9x parts, it is possible that all the output Multisynths (N dividers) may not start at exactly the same time. This effect may be different after each reset or power cycle at high temperatures. For this reason, static skew is not supported on the Si534x/7x/9x products. Dynamic skew would be used after the phase difference of two outputs is measured and a small adjustment is necessary. However, this issue is not present in the Si538x parts. For information on programming dynamic and static skew for the Si538x parts, see AN1165.
For applications that require a known input to output delay, it is recommended to use the Zero Delay Mode feature. If outputs are using the same N divider then they will always start at the same place relative to each other.
|Part||Static Skew||Dynamic Skew|
*Note that for devices with static skew, the resolution is reduced to 1/Fvco if the N-divider is an integer value.
Silicon Labs have an application note about thermal, that is AN765, you can download from https://www.silabs.com/documents/public/application-notes/an765.pdf
JESD have specified the thermal so there is official documents in JESD official website, you can download directly
JESD15-3 Two-Resistor Compact Thermal Model Guideline - Junction-to-Case
JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions — Junction-to-Board
JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information
https://www.jedec.org/ (need to registration if you don't have an account, free download)
Junction-to-board thermal resistance (θJB )
This parameter is measured in a ring cold plate fixture (see JESD51-8). This test fixture is designed to
ensure that all the heat generated in the package is conducted to the cold plate via the board.
The metric is defined as:
JB ( J B ) H θ = T − T / P
where θJB = thermal resistance from junction-to-board (ºC/W)
TJ = junction temperature when the device has achieved steady-state after application
of PH (ºC)
TB = board temperature, measured at the mid point of the longest side of the package no
more than 1mm from the edge of the package body (ºC)
PH = heating power which produced the change in junction temperature (W)
It is important to note that the θJB metric includes a contribution from the thermal resistance of the test
board. Therefore, the thermal conductivity of the board affects the measurement results. The JESD51-
8 standard requires that the metric be measured on a 2s2p board defined in JESD51-7, 9, 10, or 11.
Measurement of the board temperature very close to the edge of the package body is also intended to
minimize the contribution from the board.
Junction-to-case thermal resistance (θJCtop )
The metric is measured in a top cold plate fixture and is defined as:
( ) JCtop J Ctop H θ = T −T / P
where θJCtop = thermal resistance from junction-to-case (ºC/W)
TJ = junction temperature when the device has achieved steady-state after application
of PH (ºC)
TCtop = case temperature, measured at center of the package top surface (ºC)
PH = heating power in the junction that causes the difference between the junction
temperature TJ and the case temperature TCtop; this is equal to the power passing
through the cold plate (W)
Note: for more JEDEC standards, you can also search in this website.
What causes a CBPro warning about coupling between output clocks?
CBPro gives a coupling warning for outputs when
An example of such a warning in CBPro is “OUT1 [131 MHz] and OUT2 [125 MHz] may have coupling”
The phase noise plot of Fout1 and Fout2 will show a spur at Fspur. If Fspur is above 20 MHz it will not cause a coupling warning because most jitter specs do not integrate the phase noise above 20 MHz.
Outputs that are adjacent but “around the corner” from each other can cause a coupling warning as defined above but in practice these outputs have very little coupling. Outputs around the corner have about the same or less coupling than outputs that are spaced apart by 1 driver. The driver in between can be outputting a clock if that clock frequency is a benign clock frequency. A benign clock frequency does not generate a coupling issue to an adjacent clock.
Outputs that are spaced apart by 1 driver can still have measurable coupling but the magnitude is much less and can be ignored unless the jitter requirements are below ~180 fs rms.
The above does not apply to LVCMOS outputs because CMOS outputs, by their very nature, cause much more coupling than differential outputs like LVDS and LVPECL.
See AN862: Optimizing Jitter Performance in Next-Generation Internet Infrastructure Systems.
Fout1 = 131 MHz, Fout2 = 125 MHz
Then Abs(Fout1-Fout2) = 6 MHz; therefore a spur at 6 MHz will be on the phase noise plot of both Fout1 and fout2 and a coupling warning will be issued by CBPro.
Fout1 = 156.25 MHz, Fout2 = 125 MHz; therefore a spur at 21.25 MHz will exist but this will not cause a warning in CBPro.
For Fout1 = 131 MHz and Fout2 = 375 MHz
Then Abs(3*Fout1 – Fout2) = 18 MHz
Hence a spur at 18 MHz can be expected on the phase noise plot of both the 131 and 375 MHz outputs. CBPro will issue the warning “OUT1 [131 MHz] and OUT2 [375 MHz] may have coupling”.
Generally, the larger A + B, the smaller the spur amplitude and the lower is the jitter.
On a device with 10-12 outputs the coupling from OUT3 to OUT4, and from OUT6 to OUT7, is much less than other adjacent outputs because these outputs are around the corner from each other.
If the very lowest coupling is required, the following rules should reduce coupling effects to be less than ~50 fs rms.
The Clock Placement Wizard in CBPro only takes into account the following rules to minimize the coupling between output clocks