People sometimes mix the definitions of Time Interval Error (TIE) jitter and period jitter and easily make a common mistake of calculating TIE jitter but with period jitter formula for a spread spectrum clock (SSC). Let's denote the clock frequency as F, the down spread linear modulation as d, the modulation rate as fm, and then the increase of peak to peak value of period jitter due to spread spectrum is given by:
PJpp = d/((1-d)F);
the increase of peak to peak value of TIE jitter due to spread spectrum is given by:
TIEJpp = d/(8fm).
Take a PCIe SSC as an example: F = 100MHz, d = 0.5% (down spread), fm = 30KHz - 33KHz. It gives a PJpp of 0.05 ns and a TIEJpp of 18.9ns - 20.8ns.
Regarding DDR design, there are some clock such as 33.333333...MHz, 133.333333...MHz and 166.666666...MHz etc. Generally 33.333333MHz, 133.333333MHz and 1666.666666MHz are used to approximate value. This method will introduce more spurs and less accuracy.
Silicon Labs Multisynth technology can support 100MHz/3, 400MHz/3 and 500M/3 configuration to get exact clock with 0ppm. This configuration can reduce spurs as well.
The recommended termination is shown below.
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedance and drive strengths. A series source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance (Rs = Trace Impedance – Zs). For example, the driver impedance Zs is configured to 38 Ohm, and the trace impedance is 50 Ohm. So the Rs is 12 Ohm.
1. If you change output impedance, please change Rs accordingly.
2. Use of the complementary CMOS for one pair OUTx/OUTxb is recommended to help balance the output current surges during transitions. It will reduce the crosstalk noise for adjacent channel.
3. Generally, the lowest impedance for a given supply voltage is preferable, since it will give the fastest edge rates. The faster edge rate means more crosstalk noise to adjacent channel. If the jitter performance of adjacent channel is high priority, the higher impedance should be selected to reduce the noise.
These transients can be removed by the following process
1. Set OUT_PDN_ALL = 1 (0x0145 = 1) before any registers of the new plan are written
2. Just before the post amble is written (after all the other writes), set OUT_PDN_ALL = 0 (0x0145 = 0)
The Si5386/82/81 is internally optimized to output the LTE/CPRI frequencies with the lowest possible phase noise (jitter) using a very low noise external 54 MHz XO. For this reason the 5386 can be expected to have lower output phase noise and spurs than a 5345/95 for LTE/CPRI frequencies.
The factors that affect the Si5345 output phase noise are?
The Si5381/82/86 are intended for high performance wireless applications which require ultra low close-in phase noise and have very tight spur masks. To meet these high demands we recommend the customer use one of the 54 MHz XOs listed in table 2.3 of the recommended crystal oscillator (XO) reference manual https://www.silabs.com/documents/public/reference-manuals/si534x-8x-9x-recommended-crystals-rm.pdf. These XOs have a very low close-in phase noise profiles as well as low jitter.
Although the Si5381/82/86 device itself has many LDOs on-chip and very good PSR, XOs most of the time do not. Any power supply noise on the XO greater than the DSPLL BW will be seen at the output of the Si5381/82/86 device. For this reason it is critical to use a low noise LDO to supply power to these oscillators. An example of an ultra low noise LDO can be seen in the Si5386A-E-EVB schematics https://www.silabs.com/products/timing/clocks/wireless-jitter-attenuators/device.si5386a. Typically we recommend LDOs with less than 10 uVrms noise integrated from 10 Hz to 100 kHz.
It is acceptable to use the same LDO to supply power to the other 3.3V supplies on the SI538x device such as VDDA or VDDOx but it is not recommend to use this LDO to supply power to other ICs in your system.
For the Si5381/82/86 devices a thermal report can be viewed in the CBPro Wizard by clicking on the green temperature widget in the bottom panel, highlighted in yellow below. This tool is intended to help provide confidence for customers designing the Si5381/82/86 into higher temperature environments such as outdoor remote radiohead applications.
The report includes estimates of the typical power consumption and junction temperature (Tj) for an ambient temperature (Ta) that is input by the customer. The default Ta for typical power estimation is 25C.
The customer has the option to specify an airflow condition of 0 m/s, 1 m/s, 2 m/s depending on the airflow in their system. More airflow will result in a lower thermal resistance (ThetaJA) and lower Tj for the same frequency plan.
The power estimator always provides an estimate for the worst case Tj assuming the maximum Ta = 85C as specified in the device datasheet. The worst case condition also assumes supplies at nominal +5% voltage and takes into account increased leakage current possible at the extremes of normal process variations. This estimate is intended to give customers guardband against the maximum specified Tj for these devices which is 125C. At higher Tj than 125C datasheet performance can no longer be guaranteed.
The short answer is no.
The Reference Manuals for the Si534x/7x/8x/9x clock generator and jitter attenuator devices all illustrate single-ended external reference clocks connected by circuitry to the device's XA pin. The XB input pin is then AC-coupled to ground.
The Si5381/82 and Si5386 Rev. E Reference Manuals go further and explicitly state that "Single-ended inputs must be connected to the XA pin with proper termination on the XB pin. Because the signal is single-ended in this case, the XB input is ac-coupled to ground."
The reason why is that there is peak-detection and LOS circuitry present on the XA signal path that is not present on the XB signal path. The XA/XB interface is simply not functionally symmetric with respect to to single-ended reference clocks.
For CMOS output, usually we need to add series resistor at source end to make sure source end impedance matched since the cap load(impedance unmatched at load end), or the signal integrity will be bad. Please check part's datasheet for specific impedance of CMOS output.
Please refer to below diagram for detail information:
What is output skew?
Output skew is a user defined time delay added to each N-divider, which may be useful to adjust the relative phase of the outputs. Output skew can be categorized into dynamic skew and static skew. Static skew is a change in the output phase that is done once at power up or after a reset. Static skew is used if a known absolute time difference is required from the input to the output. Dynamic skew is a change in the output phase that can be done while the part is still running, and no reset is done.
Which products offer what type of output skew?
Within the Si534x/7x/8x/9x product line, the table below shows the availability of static and dynamic skew for the wired and wireless clocks. If applicable, the resolution of the skew is also given in terms of Fvco, where Fvco is the VCO frequency.
Under high device junction temperatures in the Si534x/7x/9x parts, it is possible that all the output Multisynths (N dividers) may not start at exactly the same time. This effect may be different after each reset or power cycle at high temperatures. For this reason, static skew is not supported on the Si534x/7x/9x products. Dynamic skew would be used after the phase difference of two outputs is measured and a small adjustment is necessary. However, this issue is not present in the Si538x parts. For information on programming dynamic and static skew for the Si538x parts, see AN1165.
For applications that require a known input to output delay, it is recommended to use the Zero Delay Mode feature. If outputs are using the same N divider then they will always start at the same place relative to each other.
|Part||Static Skew||Dynamic Skew|
*Note that for devices with static skew, the resolution is reduced to 1/Fvco if the N-divider is an integer value.
Silicon Labs have an application note about thermal, that is AN765, you can download from https://www.silabs.com/documents/public/application-notes/an765.pdf
JESD have specified the thermal so there is official documents in JESD official website, you can download directly
JESD15-3 Two-Resistor Compact Thermal Model Guideline - Junction-to-Case
JESD51-8 Integrated Circuit Thermal Test Method Environmental Conditions — Junction-to-Board
JESD51-12 Guidelines for Reporting and Using Electronic Package Thermal Information
https://www.jedec.org/ (need to registration if you don't have an account, free download)
Junction-to-board thermal resistance (θJB )
This parameter is measured in a ring cold plate fixture (see JESD51-8). This test fixture is designed to
ensure that all the heat generated in the package is conducted to the cold plate via the board.
The metric is defined as:
JB ( J B ) H θ = T − T / P
where θJB = thermal resistance from junction-to-board (ºC/W)
TJ = junction temperature when the device has achieved steady-state after application
of PH (ºC)
TB = board temperature, measured at the mid point of the longest side of the package no
more than 1mm from the edge of the package body (ºC)
PH = heating power which produced the change in junction temperature (W)
It is important to note that the θJB metric includes a contribution from the thermal resistance of the test
board. Therefore, the thermal conductivity of the board affects the measurement results. The JESD51-
8 standard requires that the metric be measured on a 2s2p board defined in JESD51-7, 9, 10, or 11.
Measurement of the board temperature very close to the edge of the package body is also intended to
minimize the contribution from the board.
Junction-to-case thermal resistance (θJCtop )
The metric is measured in a top cold plate fixture and is defined as:
( ) JCtop J Ctop H θ = T −T / P
where θJCtop = thermal resistance from junction-to-case (ºC/W)
TJ = junction temperature when the device has achieved steady-state after application
of PH (ºC)
TCtop = case temperature, measured at center of the package top surface (ºC)
PH = heating power in the junction that causes the difference between the junction
temperature TJ and the case temperature TCtop; this is equal to the power passing
through the cold plate (W)
Note: for more JEDEC standards, you can also search in this website.
What causes a CBPro warning about coupling between output clocks?
CBPro gives a coupling warning for outputs when
An example of such a warning in CBPro is “OUT1 [131 MHz] and OUT2 [125 MHz] may have coupling”
The phase noise plot of Fout1 and Fout2 will show a spur at Fspur. If Fspur is above 20 MHz it will not cause a coupling warning because most jitter specs do not integrate the phase noise above 20 MHz.
Outputs that are adjacent but “around the corner” from each other can cause a coupling warning as defined above but in practice these outputs have very little coupling. Outputs around the corner have about the same or less coupling than outputs that are spaced apart by 1 driver. The driver in between can be outputting a clock if that clock frequency is a benign clock frequency. A benign clock frequency does not generate a coupling issue to an adjacent clock.
Outputs that are spaced apart by 1 driver can still have measurable coupling but the magnitude is much less and can be ignored unless the jitter requirements are below ~180 fs rms.
The above does not apply to LVCMOS outputs because CMOS outputs, by their very nature, cause much more coupling than differential outputs like LVDS and LVPECL.
See AN862: Optimizing Jitter Performance in Next-Generation Internet Infrastructure Systems.
Fout1 = 131 MHz, Fout2 = 125 MHz
Then Abs(Fout1-Fout2) = 6 MHz; therefore a spur at 6 MHz will be on the phase noise plot of both Fout1 and fout2 and a coupling warning will be issued by CBPro.
Fout1 = 156.25 MHz, Fout2 = 125 MHz; therefore a spur at 21.25 MHz will exist but this will not cause a warning in CBPro.
For Fout1 = 131 MHz and Fout2 = 375 MHz
Then Abs(3*Fout1 – Fout2) = 18 MHz
Hence a spur at 18 MHz can be expected on the phase noise plot of both the 131 and 375 MHz outputs. CBPro will issue the warning “OUT1 [131 MHz] and OUT2 [375 MHz] may have coupling”.
Generally, the larger A + B, the smaller the spur amplitude and the lower is the jitter.
On a device with 10-12 outputs the coupling from OUT3 to OUT4, and from OUT6 to OUT7, is much less than other adjacent outputs because these outputs are around the corner from each other.
If the very lowest coupling is required, the following rules should reduce coupling effects to be less than ~50 fs rms.
The Clock Placement Wizard in CBPro only takes into account the following rules to minimize the coupling between output clocks
Si534x/7x/8x/9x output normal mode disable state has two choices: Stop High and Stop Low.
The voltage of the output positive V(Out+) = Vbias + Vpp_se, and the voltage of output negative V(out-) = Vbias - Vpp_se
2. Stop Low means that when the output driver is disabled the plus output will be low and the minus output will be high.
The voltage of the output positive V(Out+) = Vbias - Vpp_se, and the voltage of output negative V(out-) = Vbias + Vpp_se
There are two ways to control Si5332 output signal enable/disable. One is to configurate register 0xB6 and 0xB7 direclty by I2C. Another is assign GPI to control output with CBPro, but please note that these outputs can't be controled by register 0xB6 and 0xB7 if you have already assigned GPI to control some outputs enable/disable.
Crystal Reliability and Activity Dips
Activity dips can cause disruptions to networking systems and are a regrettable but chronic problem associated with the use of crystals. An activity dip can occur when there are material imperfections in the quartz. These impurities in the crystal structure cause modes of resonance (often called spurs) that are small in amplitude and not located at the fundamental, 3rd overtone, 5th overtone, etc. frequencies.
These resonance modes (or spurs) typically do not cause problems because their amplitude is so much smaller than the amplitude of the fundamental. However, they can have a very large coefficients of frequency vs. temperature. The problem occurs when an oscillator is running at the fundamental and the temperature is changing. In these conditions, the frequency of the spur will be changing much faster than the frequency of the fundamental. If the spur happens to cross over the fundamental, there can be a disruption in the crystal’s oscillation. If the temperature is ramping, this disruption will be temporary because the spur will continue to move and will move away from the fundamental.
The root cause of activity dips is the impurities in the crystal material itself and the probably of having a crystal that is prone to his problem will decrease with better control of the crystal material processing. Crystal manufacturers work very hard to keep the material as clean as possible and therefore the probability of an activity dip is very low. However, it will never go to zero and activity dips are a perennial problem for equipment manufacturers.
What can be done about activity dips? There are three alternatives:
Please note that the embedded crystal versions of the Si537x/8x/9x devices all use solution #3.
For more details on activity dips, see page 57 of the following document:
Accuracy of Phase Noise Measurements With Frequencies Below 100MHz
To ensure the accuracy of the measurements when taking phase noise plots and making RMS jitter measurements, there are times when the instrument being used to take the plots needs to be examined. In particular, the noise floor of the phase noise analyzer (which is typically the Keysight E5052B) needs to be compared to the phase noise being generated by the DUT (device under test). The phase noise of the Si534x/8x/9x devices is so low that in certain circumstances, it is lower than the noise floor of the E5052B.
For a clock that is divided by two by an ideal divider, the phase noise will go down by 6dB. Accordingly, if a phase noise plot of a 2 GHz signal is compared to a phase noise plot of the same signal divided by two, the two plots will look very similar, except that the 1 GHz plots will be 6dB below the 2 GHz plot. With continued divisions by two, the phase noise will go lower and lower until it eventually runs into the noise floor of the E5052B. At this point, the phase noise plot cannot go any lower and the measurement “saturates”. The result will be that the phase noise values will be erroneously reported to be greater than they actually are. The same will be the case for the RMS jitter value because it is derived from the phase noise data.
Though this process is somewhat gradual, it has been our experience that phase noise plots for the Si534x/8x/7x/9x devices with plots below 100 MHz in frequency are affected by the noise floor of the instrument, while phase noise plots for clock frequencies above are typically OK. This is not to say that phase noise plots taken below 100 MHz have no value. Rather the results need to examined in light of these limitations.
For a more detailed discussion of this (and aliasing of higher frequency components down in frequency), see:
If you are encountering the following error when attempting to use the Si5351-EVB，please try the following explanation to fix the issue.
Error Message in CBPro:
error running post frequency plan calculation tasks (step 1); Plan is not realizable please contact Silicon Labs support for further assitance.
This error is usually seen when you configure outputs in three frequency domains and two outputs are greater than112.5MHz.
The general criteria below were used to set the frequency plan in CBPro. This is a general model, and individual applications may require some modification.
1. The Si5351 consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate an intermediate VCO frequency in the range of 600 to 900 MHz.
Fout=Fvco/(Multisynth x R)
2. Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 900 + 0/1. This means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one of the VCO frequencies.
3. For the frequencies where jitter is a concern make the output Multisynth divide ratio an integer. If possible, make both output and feedback Multisynth ratios integers.
4. Once criteria 2 and 3 are satisfied, try to select as many integer output Multisynth ratios as possible.
OUT1=155.25MHz, OUT2=125MHz and OUT3=94MHz.
CBPro calculates VCO_PLLA=155.25M*4=621MHz and VCO_PLLB=125M*6=750MHz.
But OUT3=94MHz>93.75MHz(750MHz/8), Multisynth divider=750/94=7.9787<8, so the frequency plan cannot be realized.
If OUT3≤93.75MHz, The frequency plan can be realized by Multisynth divider ≥8.