How do I disable or enable the clock to a peripheral?
The APB clock can be enabled or disabled to a set of peripherals using the Clock Control (CLKCTRL) module.
For modules that run from the APB clock, disabling the clock to the peripheral will completely disable the module.
For modules that run from an alternate clock source like the RTC0 Oscillator, disabling the clock to the peripheral will disable the clock to the registers only; the module will continue to run using the register's previous settings before firmware disabled the clock. Because these modules run from two different clock domains, there is often a clock synchronization step required between the APB and the module clock, leading to a two-peripheral-clock delay between writing a value to a register and reading it back.
More information on the device clocking can be found in the device reference manual. Device documentation can be found here: www.silabs.com/32bit-mcu.
More information on each of these clock sources can be found in AN663: Precision32 MCU Family Clocking Options, the SiM3C1xx data sheet, and the SiM3U1xx/SiM3C1xx reference manual. The 32-bit MCU application notes and device documentation can be found here: www.silabs.com/32bit-mcu.
More information on each of these clock sources can be found in AN663: Precision32 MCU Family Clocking Options, the SiM3U1xx data sheet, and the SiM3U1xx/SiM3C1xx reference manual. The 32-bit MCU application notes and device documentation can be found here: www.silabs.com/32bit-mcu.
What is the maximum clock rate for the ECI EPCA/PCA input?
When the external clock input (ECI) is selected as the EPCA clock source, the clock divider decrements on falling edges or both rising and falling edges of the pin. The ECI pin is synchronized to the selected AHB clock in this mode. The maximum clock rate for the ECI external clock input is the APB divided by 4.
What are the concerns when using a system clock faster than 25 MHz?
When using system clock speeds greater than 25 MHz, take the following into consideration:
Set the FLSCL SFR for the appropriate clock speed. The FLSCL register determines the Flash access timing. The Flash memory is rated for 25 MHz access and Flash timing must be adjusted for higher system clock speeds. The prefetch engine on these MCUs enables the code execution to keep up with the higher clock speeds.
The maximum slew rate for inputs and outputs is dependent on the trace capacitance. For pins that are toggling at higher speeds, minimize the trace lengths to reduce the trace capacitance and ensure a higher quality signal.
Certain devices are capable of running at speeds greater than 50 MHz. When running faster than 50 MHz, VDD must be higher than 3.0V. The on-chip VDD monitor threshold for these devices is 2.7V. If VDD monitor functionality is required, use an external VDD monitor.
The Si533xx data sheet shows current consumption at a given frequency, what is it at other frequencies?
The IDDOA and IDDOB current consumption is consistent over the operating range of output frequencies for the differential outputs; LVPECL, LPPECL, LVDS, HCSL and CML. The current listed in the data sheet should be used for any valid frequency.
IDDOA/B current consumption does depend on frequency for CMOS output operation, below shows how IDDOx current changes with frequency.
The legends show the Output logic, drive strength and supply voltage. As an example CMOS-24-3.3V is a CMOS output, 24mA drive and 3.3V operation. The drive current is per output.
The IDD current has minimal change vs frequency as follows
My Si5319/Si5324/Si5326 won’t lock, how can I isolate the problem?
Additional causes for failure to lock, LOL or a LOS condition included:
Reserved bits are overwritten. There are “Reserved” bits in the registers settings which cannot be overwritten. As example, the bottom 4 bits in Register 2 are “Reserved” and should always be set to 0010 when the upper 4 bits are set.
There are also reserved registers which are not mentioned in the Users Manual, these should not be overwritten.
DSPLLsim should be used to generate frequency plans and to ensure correct register settings.
The Input Clock exceeds 0 or VDD. This is a more common problem for single ended CMOS inputs which may have ringing or overshoot. In order to avoid exceeding 0 or VDD and to optimize signal integrity, a single ended CMOS input should be attenuated using Figure 41 in the Si53xx reference manual and as shown below.
The Input Clock has slow rise and fall times. The minimum rise and fall time is 11 ns. This can be a more common problem for slower clock inputs such as 8 kHz which is most likely a CMOS signal. CMOS signals can be loaded down when using 50 ohm matching circuits and it’s important to understand the source drive capability.
The Input Clock has runt pulses. The Si5319 family can translate and clean-up a gapped clock but runt pulses are not tolerated.
Free Run Mode selected: When incorporating FreeRun, it’s always best to use “Manual” clock selection and select CKIN2 until CKIN1 becomes valid and stabile. There are two reasons for doing so. 1) If “Autorevertive” and CKIN1 is selected as the priority input, then noise on CKIN1 may cause the PLL to remain on CKIN1 in which case the PLL may not enter FreeRun. 2) If CKIN1 has runt pulses, then LOS can be alarmed and the PLL will remain in FreeRun mode, even once CKIN1 is clean of runt pulses.
The Differential Input, CKINp/N, is incorrectly set, eg the negative input is set to ground, or there are large differences in VICM; AC coupling is recommended to eliminate VICM issues.
The Differential Input Clocks have a large phase error. A differential input is nominally 180 degrees out of phase, large errors could cause glitches or erroneous clock signals.
The FOS alarm is unintentionally set and alarmed. The Si5319 family will not lock up if the FOS alarm is set and FOS is alarmed, double check the FOS alarm register and settings (see in the Si53xx Reference Manual).
DHOLD is set. Nominally the Digital Hold is automatically set such as when the valid input clocks become inactive and the Si5326 would go into hold, DHOLD. However the DHOLD can also be manually be set by writing to Register 03 bit D5.
Clock select is not set as expected or Input Buffer is powered down. Double check the input clock selection method is the one required and the input buffer has not been disabled, Register 11, PD_CK1 and PD_CK2 (0 = enabled).
How should the unused input and outputs be terminated on the Si533xx series buffers?
CLK0/1: The clock inputs, CLK and /CLK, are internally biased as shown in Figure 1 to reduce possible chatter or noise on the outputs under a “no clock” input condition. CLK and /CLK should be unconnected if not used.
OE: The OE has an internal 25 Kohm pull-up resistor and can be unterminated for active outputs. However for troubleshooting purposes it may be desirable to enable and disable the outputs using the OE feature – in this case OE would be terminated to GND through a resistor such as 1 Kohm. The resistor would normally be “Do Not Populate”.
DIVA/B: The DIVA/B pins have internal 25 Kohm pull-up and pull-down resistors, setting an internal bias to VDD/2. For a midlevel state the DIV pin(s) would be left open. A smaller value resistor, such as 1K or lower, should be used when terminating DIV to VDD or GND – a 10K pull-up or pull-down may not achieve the appropriate logic levels.
SFOUTA1/0, SFOUTB1/0: The SFOUT pins have internal 25 Kohm pull-up and pull-down resistors, setting an internal bias to VDD/2. For a midlevel state the SFOUT pin(s) would be left open. A small value resistor, such as 1K or lower, should be used when terminating SFOUT to VDD or GND – a 10K pull-up or pull-down may not achieve the appropriate logic levels.
CLKSEL: The CLKSEL has an internal 25 Kohm pull-down resistor which selects the CLK0 inputs when left unconnected. CLKSEL requires a logic high to select the CLK1, such as a 1K pull-up or smaller to VDD.
LOS: Loss of signal is an alarm output pin and should not be terminated to VDD or GND when not used. In some applications LOS can be connected to CLKSEL, allowing automatic switching to CLK1 with no input on CLK0 (autorevertive switching). A buffer should be used if LOS is used to drive an LED.
Q/Qnot, ClockOutputs: Unused differential pair and single ended clock outputs can be unterminated. If unused outputs are routed then termination at the “receiver” is recommended to reduce possible noise and crosstalk issues. Differential outputs should terminated in like manner, e.g. if one output is used the other should not float and must be terminated in a similar method.