Is it really that important to have impedance-controlled clock traces?
Standard layout practice dictates the use of traces with a characteristic impedance of 50W. In order to minimize reflections resulting in overshoot/undershoot or stair-stepping, either the driver output or receiver input impedance must be within the range of the trace impedance. CMOS signals are defined as high input impedance, so the burden of impedance matching lies on the output driver end.
Figure 1 below illustrates the overshoot and stair-stepping phenomena, which occur when the driver impedance is significantly lower or significantly higher, respectively, than the trace impedance.Note that excessive overshoot can result in erroneous clock edges and excessive stair-stepping can result in delayed clock edges.
Figure 1. Effects of Overshoot and Stair-Stepping on Clock Edge
I'd like to use the PCIe CLKREQ_n as an enable/disable gate for my Si533x PCIe clock output.
The Si533x OEB pin is active low enable (active high disable), whereas the PCIe CLKREQ_n signal is an active high enable signal. To use CLKREQ_n as an enable/disable gate for a Si533x output, you must invert CLKREQ_n for it to be PCIe-compliant.
What are some troubleshooting suggestions if an Si57x oscillator does not acknowledge?
Here are some troubleshooting suggestions if an Si570 or Si571 oscillator does not appear to acknowledge the I2C bus master.
(1)Double-check that the I2C address is correct.
(2)Verify that the I2C transaction logic is correct using a bus logic analyzer or oscilloscope.
(3)If the transaction logic appears correct, examine the I2C bus waveforms on an oscilloscope. Look for potential issues related to signal integrity (interference, noise, rise/fall time) and signal level.
(4)In particular, check that the logic LOW signal voltage is sufficiently low for the Si570/571 to recognize it. See Timing Knowledge Base article #312479, 'Si57x I2C Voltage Level Translation', /display/2/kb/article.aspx?aid=312479&p=12887.
(5)Finally, we would strongly encourage you to buy an evaluation board since you can independently control and test Si57x and other I2C-programmable oscillators with it, compare I2C bus activity, and the software is very useful in any case. Please see the Si5xx-PROG-EVB description at http://www.silabs.com/products/clocksoscillators/Pages/Si5xx-PROG-EVB.aspx. These EVBs are available from our distributors such as Avnet, DigiKey and Mouser.
Termination scheme for single ended clock driving a differential receiver
In certain application, there might be a need to use a Si5350/51 for generating all of the clocks for the system. If Si5350/51 is required to drive a receiver of differential format (HCSL, HSTL/SSTL, LVPECL, LVDS, CML etc.), the circuit scheme (shown below) can be used:
The Tables below lists the R1, R2, R3 and R4 values for popular standards:
Termination option to use Si5335 to drive a 1.2V single ended receiver
Please use the implement schematic with the following steps:
The steps are:
1. Choose 3.3V, CML output buffer at the Si5335 output 2. Terminate 100 ohms between CLKi and CLKi#. 3. As shown above, AC couple the CLKi node using a 0.1 uF cap 4. Set up a DC bias of 0.6V from a 1.2V supply as shown above. 5. Now, a clock signal of VLOW = 0.1V and VHIGH = 1.1V is set up for the receiver.
Si5330x can only be used for clock buffering applications and cannot be used for data buffering. The specification shown below implies the same.
Even though a Non-Zero-Delay Buffer implies that the chip will buffer any pattern, the above specification means that data patterns cannot be handled when a data high or a low condition occurs for longer than 1 uS.
This limitation means that in the Si5330x family buffers cannot be used for data buffering and can only be used for clock buffering.
This article lists the requirements for clocks used for PCIe cabling and the tools provided in Si labs PCIe clock generators and buffers to meet them.
The reference clock requirements for PCIe cabling:
The reference clock architecture for PCIe cabling:
The terminations highlighted in blue (in the figure above) are not required for Si Labs PCIe clock generators and buffers.
Tools provided in PCIe clock generators and clock buffers to meet PCIe cabling requirements:
1. The VDIFF_MAX is flexible and can be increased to compensate for cable losses/attenuation. 2. Skew between CLK+ and CLK- can be tuned to compensate for any impedance mismatch between the clock pair (to reduce ring back). 3. More than 50% margin for jitter.
Can we combine LOS signals of multiple Si5330 buffers?
Consider the following truth table Control
Consider the following truth table Control Signal for LOS1
Control Signal for LOS2
Conduction path through LOS1
Conduction through LOS2
Voltage at Node N
1. LOS at Node N will be triggered ONLY if both Si5330-1 and Si5330-2 lose input clock. 2. If either LOS1 or LOS2 becomes high, Node N will still be Low i.e. IT WILL NOT TRIGGER LOS. 3. Therefore, if you need to monitor both LOS1 and LOS2 independently, you will need to use two separate pull up resistors
Hence combining LOS signals of multiple Si5330 devices is not recommended.
This article provides a method to calculate the increase in cycle to cycle and period jitter due to Spread spectrum clocking.
Impact of SSG on period jitter
The impact of SSG on period jitter is relatively straight forward. If the maximum period jitter of a clock without SSG is PJMAX:
Impact of SSG on cycle-cycle jitter
While period jitter is independent of the modulation profile, cycle-cycle jitter depends significantly on the modulation profile. This article assumes that the modulation profile is linear which is true for Si Labs clock generator ICs.
The additional cycle-cycle jitter due to SSG is given by:
SSG = 1/(Fclk2 * 4* MR*SS%) for clocks with center spread.
SSG = 1/(Fclk2 * 2* MR*SS%) for clocks with down spread.
Generally, when it is claimed that SSG does not increase jitter, it means cycle-cycle jitter because, the increase is typically less than 10 pS. But the increase in period jitter is significant and needs to be accounted for.
SS% = Spread percentage fraction (i.e. 1% = 0.01 in the calculations)
Si5330 buffers also come in a single ended HSTL mode. Such buffers can drive a differential HSTL receiver with a small modification to the termination recommendation in AN408 (Please refer to Figure 13 on page 10 in AN408 ) shown below:
The modification is as shown below:
The above termination will enable single ended HSTL outputs from Si5330 buffers to drive differential HSTL receivers.
Si5350/51 buffers have a ZS (source impedance) of 85 ohms (typical) and some applications may need these buffers to drive a 50-ohm impedance trace. Is it possible to match impedance when Zs > Z0? Yes, if the application can compromise on the voltage swing.
This article shows a method to realize impedance matching when Zs > Z0.
The method is as shown below:
The resistance highlighted in the blue region helps reduce the source impedance of Si5350/51 and is chosen such that:
1. The IOH (current drawn from the output buffer) increases significantly. a. IOH = VDD0/215 which works out to ~15mA , ~12mA at 3.3V and 2.5V respectively.
2. There will be reduction in signal swing (a typical loss of 40% swing) a. VHigh = (130/215)*VDDO which works out to 2V, 1.5V at 3.3V and 2.5V respectively.
Therefore, this solution only applies to a special circumstance.
The special circumstance under which this solution is feasible:
1. The receiver should have VIH
MIN lower than 2V (VDD0 = 3.3V) or 1.5V (VDDO = 2.5V).
Hence, if the receiver VIH specifications allow for a signal swing reduction, it is possible to use higher impedance source to drive a lower impedance trace. Specifically, it is possible to use a Si5350/51 buffer to drive a 50-ohms trace.
How do I accurately calculate an estimate of overall clock tree jitter when using a combination of clock generators and/or clock buffers?
There are several calculation methods that are useful in estimating overall clock tree jitter when a combination of clock sources and/or clock buffers are used. The key is in understanding each device’s jitter specs and how to combine this data in an accurate and meaningful fashion. For example, when adding RMS jitter specs that assume a Gaussian jitter distribution, it is not accurate to simply add up the jitter values. In this case you must use the Root-Sum-Squared (RSS) method which is simply the square root of the sum of all the individual values squared. Also, if the available jitter spec is given in terms of phase noise levels at specific carrier offsets, this data may need to be frequency scaled and converted to an RMS jitter value before used. For specific details and application examples of these methods, refer to AN739 for a complete explanation.