What is the difference between Digital Hold and VCO freeze?
To implement the holdover function, the Si5317, Si5319, Si5327 and Si5375 have VCO freeze. However, the Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5376 all feature Digital Hold for holdover. The distinction between VCO freeze and Digital Hold is that Digital Hold provides history registers that let the user change the holdover behavior to suit the particular application. VCO freeze does not have these registers and the holdover behavior is hard wired. Nonetheless, VCO freeze does keep a holdover history that is unspecified and is roughly one second. For details on Digital Hold and its history functions see section 6.6 of the Reference Manual, which can be downloaded from the Silicon Labs website:
When using Si537xDSPLLsim with an Si5374/75/76, what is Advanced Mode and when should I use it?
When Si537sDSPLLsim creates a new frequency plan and register map, it searches the potential solution space for the best solution. For typical applications, Si537xDSPLLsim will be able to find a single good solution. However, there are situations where some characteristics of a solution need to be traded off against other attributes of a different solution. Since there are usually a large number of potential solutions, it stands to reason that Si537xDSPLLsim will not always be able to pick the best compromise as intended by the user.
As a result, Si537xDSPLLsim makes it easy for the user to select a compromise by hand. This is done by checking the “Use Advanced Mode” box in the Configuration window when entering a new frequency plan.
In the next window (Search Parameters), the user can search and sort through the various solution for each of the relevant DSPLLs. The user also has the option of unchecking the Enable Automatic VCO Management check box. For a discussion of automatic VCO management, see Appendix K of the Reference Manual, which can be downloaded from the Silicon Labs web site:
What is the recommended approach to terminating differential transmission lines so as to minimize Common Mode noise?
There are many output clock formats such as CML, LVDS, and LVPECL that are routed and terminated differentially. This is usually illustrated as a pair of single-ended nominal 50 Ω transmission lines (one for each polarity) terminating in to an ideal 100 Ω resistor at the far end or receiver end of the circuit.However, this only terminates the Differential Mode (DM) signal.Any skew or imbalance will result in Common Mode (CM) noise which is not terminated.
The ideal termination can be improved upon by splitting the terminating resistor in to 2 each nominal 50 Ω resistors and then AC-coupling the center-tap to GND via a capacitor.This minimizes CM noise by terminating both DM and CM.A discussion of this general approach can be found for example in “Differential Termination” by Dr. Howard Johnson, originally published in EDN magazine, July 5, 2000, http://www.sigcon.com/Pubs/edn/DifferentialTermination.htm.
Finally, a word about internal terminations: Many SOCs and FPGAs support internal differential terminations. However, they usually do not support CM termination or give pin access to the center-tap. Therefore, if CM noise is an issue, it is best to disable the internal termination if possible, and use an external differential split termination instead.
My I2C bus is operating at a different voltage than my jitter attenuating PLL. Is this OK? If not, how can I do the voltage translation?
There are ESD clamp diodes on the I2C pins of the jitter attenuating PLLs. If the PLL is operating at a different voltage than the other members of the I2C bus, the I2C logic levels may be incorrect because of the clamp diodes. In this case, an I2C voltage translation device can be used. There are number of such devices available and two examples are listed below:
Manufacturer and device part number: NXP Semiconductor GTL2002 Texas Instruments PCA9306
How can I monitor the XAXB (or OSC_P/OSC_N) oscillator frequency?
The output of the XAXB oscillator of an Si5319, Si5324, Si5326, Si5327, Si5368 and Si5369 can be routed to the CKOUT pins to verify and measure the frequency of the oscillation. This is done by modifying register bits to put the device into both Free Run and Bypass modes. Free Run routes the output of the XAXB oscillator to CKIN2 and Bypass mode routes CKIN2 to all of the clock outputs. This approach can also be used for the corresponding OSC_P/OSC_N inputs of the Si5374, Si5375 and Si5376. To do this, perform the following register writes for the Si5324, Si5326, Si5368, Si5369, Si5374 and Si5376:
Register write Addr, decimal value, hex comment 0 76 Bypass and Free Run modes 4 96 enable automatic clock selection 11 4d turn off all clock input buffers, except CKIN2
Because the Si5319, Si5327 and Si5375 do not support automatic clock selection, the above write to register 4 will not work. Instead the CS pin (pin 21 for the Si5319 and Si5327 and pins D1, A6, F9 and J4 for the Si5375) should be placed at logic one.
The technique should not be used for measuring the XAXB oscillator jitter because Bypass mode is not internally implemented with a low jitter signal path.
Bypass mode does not work with the CMOS output format. As a result, if the outputs are CMOS, it will be necessary to change the output format by writing to the corresponding SFOUT register.
What are the advantages and disadvantages of using the Si5374, Si5375 and Si5376 as quad free running XOs?
The Si5374/75/76 can all be configured to implement four asynchronous, free running, programmable XO’s with four different and independent output frequencies and different output formats. Beyond the usual cost, power and PCB real estate considerations, there are additional advantages and disadvantages to using an Si5374/75/76 instead of four programmable XO’s, like the Si570. Si570 is unique in that it also has extremely low output jitter that is comparable to the Si53574/75/76. The below lists some items which may help in the decision making process:
1. Using the Si5374/75/76 requires a low jitter OSC reference, stability and accuracy are tracked. The Si570 is self contained.
2. The accuracy and drift behavior of the Si5374/75/76 are entirely due to the drift and accuracy of its OSC_P/OSC_N reference oscillator.
3. The Si5374 and Si5376 each have two outputs which can be programmed for different (but integer related) output frequencies. The two outputs also have independent programmable output format registers (SFOUT).
4. The Si570 can be factory programmed to power up to a desired output frequency. The Si5374/75/76 registers are volatile and always need to be programmed at power up.
5. The output frequency of an Si570 can be dynamically altered during operation using register writes. The Si5374/75/76 is limited to static output frequencies.
6. Using an Si5374/75/76 as an XO concentrates the physical locations of the clock source to one area. For some applications this may increase the routing complications and PCB etch run lengths.
In addition to the above considerations, it is important to examine the relevant data sheets and applications notes.
I'm seeing a high failure rate when I program blank Si5338's or Si5356.
If you're using the Field Programmer application that was installed with ClockBuilder Desktop v5.0 or v.5.1, then the solution is to install ClockBuilder Desktop version 6.0 or later (available online Jan 2013). If using v6.0 does not fix the problem, contact technical support.
We apologize for any inconvenience, and if you're not able to wait until v6.0 is online, you may access v6.0 beta at the link below. Note that this is a beta version, and Silicon Labs recommends using the official release for anything other than prototyping.
What is the difference between Si570/571 commands RECALL versus RST_REG?
The Si570 and Si571 I2C-programmable oscillators have 2 somewhat similar operations available: RECALL asserted via Register 135 bit 0, and RST_REG asserted via Register 135 bit 7. Both operations will force the device back to it's factory installed or start-up configuration without requiring power cycling. The differences are as follows:
1. Asserting RST_REG resets all the registers which interrupts the I2C state machine and I2C communication. Therefore, asserting RST_REG is generally not the recommended approach for starting Si57x devices from initial conditions.
2. By contrast, asserting RECALL reloads the NVM contents in to the operating registers withoutinterrupting the I2C state machine. Therefore, asserting RECALL is the recommended approach for starting Si57x devices from initial conditions.
What is the recommended approach to implement Si57x I2C voltage level translation?
The Si570 and Si571 digital I/O, including SCL and SDA, are based on standard foundry I/O cells which have not been modified for I2C's input voltage requirements. This is why SDA VIL = 0.5V max. Therefore, Si57x devices are compatible with a directly bussed I2C master but not necessarily via an I2C bus extender or other device that yields a 'buffered' LOW.
The Silicon Labs Si5xx-PROG-EVB, which supports multi-VDD testing of the Si514 and Si570 devices, and other similar EVBs, uses a TI PCA9306 instead of a PCA9517. This is a switch as opposed to a buffer and can yield lower logic LOWs. This is the recommended approach to implement Si57x I2C voltage level translation.
What is the memory volatility of the Si570 and Si571 oscillators?
The IC used in the Si570 and Si571 oscillators contains the following memory: NVM = 128 words (registers) x 8 bits, non-volatile write-once, programmed at factory, inaccessible by I2C RAM = 256 words (registers) x 8 bits, volatile, many registers reserved or inaccessible by I2C User tuning information written in to RAM will be sanitized after power is removed.
If you need a formal Letter of Volatility from Silicon Labs, you will need to request it from the oscillators product manager.
The coplanarity spec for oscillators is shown as a flatness tolerance on the outline drawing in the datasheet. For example, the coplanarity spec for the Si570 would be dimension CCC = 0.10 (mm) max as shown in Figure 8 and Table 16 in the Si570 Rev. 1.3 datasheet, https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf.
The time that it takes to complete an ICAL has significant variation from ICAL to ICAL. The ICAL time is also very dependent on the selected loop BW. The following two plots were taken with the following conditions: 1. Input clock = 19.44 MHz 2. Output clock = 622.08 MHz 3. Si5326 4. 114.285 MHz crystal 5. 30 ICALs were done at each loop BW value 6. ICAL time defined by the duration of LOL (loss of lock)
The data for the two plots is the same. The top plot is a linear scale, while the bottom plot is logarithmic.
From a typical phase noise plot taken at room temperature, you can estimate the expected jitter in either very hot or very cold conditions using the following typical plots of jitter versus temperature. The test conditions were:
For an Si5315/16/17/19/23/24/26/27/66/68/69/75/74 what causes entry into holdover? Will the loss of lock alarm (LOL) cause entry into holdover?
A necessary prerequisite for entry into holdover is that the device must have previously been locked to a clock source. Once that has occurred, if at some point in the future there is no valid input clock, the device will enter holdover. A clock is valid if none of its alarms are active and if it is the currently selected clock input. The two possible clock input alarms are LOS (loss of signal) and FOS (frequency offset). Clock selection can be either automatic or manual and manual clock selection can be implemented either using the clock select register or the device’s pins. For example, if clock input 1 is manually selected and there is no clock present on clock input 1, the device will go into holdover. Entry into holdover is not caused by the assertion of LOL (loss of lock). If a device is locked to a clock input and the clock input’s frequency changes, the device’s output clock will track the frequency change in order to maintain lock. If the frequency changes by an amount that is large enough, the device will lose lock and the loss of lock alarm will become active. However in this scenario, without the activation of one of the clock input alarms, the device will not enter holdover. In summary, LOL does not cause entry into holdover; but entry into holdover forces LOL to be active. Some of the features mentioned above may be available on some devices, but not others. For details on what is available for a particular device, see the individual data sheets. For more details on holdover and clock selection logic, see the Family Reference Manual (Si53xxReferenceManual.pdf).
There is a DSPLLsim bug that causes problems with opening register map files when DSPLLsim is initially launched. The problem only occurs immediately after DSPLLsim is launched and goes away as soon as any register map at all has been opened. Here is the work around:
1. After launching DSPLLsim, in the DSPLLsim Start-up wizard, open any frequency plan whatsoever. The easiest way to do this is to click on the “Si5326 default settings” button and proceed from there. 2. Once the default register map has initialized the software, any of the previously saved register map files can now be opened by clicking Options > Run Start-Up Wizard in the menu and selecting “Read from register map file”.
Notes: 1. The bug and work around are the same when connected to and when not connected to an eval board. 2. Si537x DSPLLsim does not have this problem.