What is the typical temperature rise of Si5xx devices?
·In still air, when directly soldered to a multilayer board, the temperature rise from self-heating, as measured on the device surface, is about 9°C. If the device is mounted in a small spring latch socket, temperature rise may increase to somewhere between 20°C to 30°C.
·ΘJA has been simulated to be 84.6 ºC/W under natural convection using a JEDEC 4 layers 2S2P board.
·ΘJA has been estimated previously to be approximately 40 ºC/W based on measurements using our evaluation boards.(Note: The eval board layout, traces, connectors, etc. drop the lid case temp from an expected simulated 23 ºC temp rise to a cooler measured 9 ºC temp rise.)
What is the maximum junction temperature for the Si5xx devices?
The absolute maximum operating junction temperature for the die used inside the Si5xx series is TJ = 150 ºC. However, this is an Absolute Maximum Rating. (Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.) The maximum design temperature is TJ = 125 ºC. Therefore, the recommended maximum TJ = 125°C.
What is the MSL (Moisture Sensitivity Level) of the ceramic packages?
Per to the JEDEC specification (IPC/JEDEC J-STD-020C, July 2004), the devices are classified as MSL 1, which refers to the least moisture sensitive classification level.
Although the JEDEC specification applies to “non-hermetic” (e.g., plastic) packaging, Silicon Laboratories tests and guarantees our oscillators’ products’ Moisture Sensitivity Level (MSL) according to the JEDEC specifications noted above.
Should we terminate an unused diffrential output clock polarity?
Yes, even if a differential output clock is being used to provide only one single-ended output clock you should always terminate the unused polarity in the same fashion. Differential output buffers for formats like CML, LVDS, and LVPECL typically use common mode voltage feedback to help bias the output circuit. Keeping the output amplifier balanced is key to the CM feedback circuit operating properly.
This holds true for both DC-coupling and AC-coupling applications. So for example if an Si530 or Si550 LVPECL output oscillator is being AC-coupled to supply only 1 single-ended clock, both sides should be near-end biased identically and AC-coupled to similar loads.
My signal has no preamble so I cannot use the FIFO mode. I tried to use the direct mode or raw mode and it works but the output signal is jittery. Is there a way to improve this?
Yes. The speed of the clock recovery circuit can be improved by setting the CRFAST to 7. Even if the transmitted signal does not contain preamble pattern it is possible that the incoming noise or part of the payload can be interpreted by the chip as ‘1010…’ pattern and the receiver switches to slow clock recovery mode. To avoid this set CRSLOW to 7. CRFAST and CRSLOW can be found in the Clock Recovery Gearshift Override register at address 1Fh.
For both clock inputs and outputs, the best approach is to disable the unused port and leave the unused clock pins as“no connect” (i.e. a NC). The method of doing this differs between the serial port controlled devices and the pin controlled devices:
Serial port controlled (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375): If the ith clock input port is unused, the PD_CKi bit in register 11 should be set. This will slightly reduce the power draw and disable the clock input. If the ith clock output clock port is unused, SFOUTi_REG in register 5, 6 or 7 should be set to 001 for Disable. Again, this will disable the output port so that the pins can be left as NC.
Pin controlled devices (Si5315, Si5316, Si5317, Si5322, Si5323, Si5365, Si5366): Unused clock inputs can be left as no connect. If they are connected only to the PCB pads, bypass capacitors to ground are not required. If they are connected to etch runs, caps to ground are recommended. No external pull up or pull down resistors are needed.
Because the SFOUT0 and SFOUT1 pins apply to all of the outputs, pins other than the SFOUT pins must be used to individually disable specific output ports. For both the QFN and TQFP devices, if the DBL_2BY pin is at the M level (or is NC), CKOUT2 will be disabled. For the TQFP devices (Si5365, Si5366), CKOUT5 can be disabled by setting the DBL_FS pin to H. CKOUT3 and CKOUT3 can be disabled as a pair by connecting the DBL34 pin to the H level.
How do I estimate power consumption of the Si533x (or Si5356) with my custom frequency plan?
The Si533x-EVB and Si5356-EVB come with an in-circuit current measurement and reporting feature. To use this feature:
1. Use ClockBuilder Desktop to set up your frequency plan as needed. 2. Make sure to click the 'Apply Values to Register Map' button on any tab that is changed. 3. Click Measure in the Power tab.
After a few seconds of measurement on the EVB, ClockBuilder Desktop will provide current consumption for VDD and each of the VDDOx supplies. The VDDOx measurements are done with approximately a 1pF load. If your application requires a bigger load, additional VDDOx current can be estimated using the equation below:
IDDOx_additional = Vpp * fout * C,
where Vpp is the peak-to-peak swing of the output signal and C is any additional load capacitance.