Is it possible to take cumulative small frequency steps instead of a large frequency step and thereby avoid re-calibration?
No, it is not possible.The DCO for the Si570, Si571, Si598, and Si599 devices is calibrated and centered to allow for -40C to +85C operation at a particular DCO frequency. Making a small frequency step, by revising RFREQ only, does not re-calibrate or re-center the DCO. Therefore, a series of cumulative small frequency steps, higher or lower than the calibrated center frequency, will eventually “rail” the DCO causing the device to reset and reload NVM.
The datasheet spec for Delta Frequency for Continuous Output is +/- 3500 ppm “From center frequency”. Actual performance, especially at room temperature, will typically be much better than this. However, to guarantee proper operation, one should always re-calibrate for frequency steps > +/- 3500 ppm.
I am using either the Si5374 or the Si5375. How can I determine if my application will require a heat sink or forced air flow?
Answering this question involves performing a thermal analysis based on the details of the intended application. This is an example based on the following assumptions:
An Si5375 operating with Vdd = 2.5V, with four LVPECL outputs, no air flow (still air) and no heat sink
First, some observations:
From the Table 2 of 1. The current draw of the Si5374/75 device is constant over the Vdd range. This means that the maximum current draw in Table 5 of the data sheet can be multiplied by Vdd to produce a power value.
LVPECL outputs draw the most power, followed by CMOS; with LVDS and CML being the least power hungry output formats.
The thermal analysis:
From the Table 2 of the data sheet, the worst case supply current will be 980 mA, which results is a worst case power draw of 0.98A*2.5V = 2.45W
From Table 5 of the data sheet, the still air thermal resistance from the junction to ambient is 16 degC/W,which results in a 39.2 degC rise above the ambient air temperature, noting that 39.2degC = 16degC/W*2.45W.
From Table 5 of the data sheet, the maximum allowed junction temperature is +125 degC. This means that for the above operating conditions, the maximum still air ambient temperature is +85.8 degC.
If this is maximum operationg temperature is not acceptable, there are a number of possible solutions:
Lower the Vdd to 1.8V (nominal), which will reduce the device power. Note that at 1.8V, the LVPECL output format is not available.
Change the output format to LVDS, in which case the current draw for CMOS outputs can be used as an upper bound to the Si5375 current draw.
Use a fan to introduce airflow and thereby reduce the thermal resistance from the junction to the ambient air,as indicated in Table 5 of the data sheet.
Put a heat sink on the Si5375. The following is a link to a recommended heat sink:
I am using one of the below listed devices with a single-ended LVCMOS clock input. How should I make this connection and what issues should I consider? Si5315, Si5316, Si5319, Si5322, Si5323, Si5324, Si5325, Si5326, Si5365, Si5366, Si5367, Si5368
The inputs to these devices are very high speed comparators that are designed to work at frequencies considerably higher than what LVCMOS supports. They also must operate with a peak-peak swings that are considerably smaller than a rail-to-rail LVCMOS output. This means that the inputs are very sensitive to input clock signals with poor signal integrity (SI). Here is a suggested circuit:
For these devices, we do not publish the crystal specifications that are required in order to guarantee oscillation.Instead, we have qualified a number of crystals from various vendors and listed them in the documentation.The reason we adopted this approach was that the selection of 3rd overtone crystals is a bit more complicated than it is for fundamental mode crystals. See Appendix A of the Any-Frequency Precision Clocks Family Reference Manual for a list of approved 114.285 MHz crystals.Appendix B includes a discussion of crystal and reference frequency selection and their effect on output jitter.
Also, even though AN591 is specifically directed towards the Si5315 and Si5317, its information applies equally well to the other devices in the family.In addition to listing both the approved ~40 MHz and 114.285 MHz crystals, it also has crystal selection information and guidelines.
For further information on crystal and reference frequency selection, please contact Silicon Labs.
Can I use a crystal instead of an XO with the Si5374 and Si5375?
NO, this cannot be done.A stand-alone external oscillator must be used.See the Si5374 and Si5375 data sheets and the Any-Frequency Precision Clocks Family Reference Manual for the external oscillator requirements.
Duty cycle is traditionally specified as a percentage of the clock cycle.This might make sense for a fixed frequency crystal oscillator; but it does not for a DSPLL with a wide range of possible input frequencies.
The input duty cycle specification for these devices (CKNdc) provides the minimum positive or negative pulse width (noting that the active edge of the clock is the positive edge).The CKNdc duty cycle specification is 40% to 60% or 2ns, whichever is smaller.To explain this, consider the following example:
For a DSPLL input frequency of 1 MHz, the 40% to 60% duty cycle requirement says that the minimum pulse width is 40% of 1us, which is 400 ns.For relatively low frequency clock input signals with a duty cycle that is far off of 50% (e.g. a frame sync pulse), this is an unnecessary restriction.For this reason, we simply say that the minimum pulse width is 2ns (which is much less than 400 ns, in this case).
However, at high frequencies the 2ns value does not apply.With an input frequency of 700 MHz, a 2 ns minimum pulse width clearly makes no sense because the period of a 700 MHz clock is 1.43 ns, which is small than 2 ns.So at high frequencies the 40% to 60% rule applies.
The point at which one rule switches to the other is at 200 MHz because the period of a 200 MHz clock is 5 ns and 40% of 5ns = 2 ns.
Spread spectrum can be enabled on any clock output that uses PLLA as its reference. Valid ranges for spread spectrum include -0.1% to -2.5% down spread and ±0.1% to ±2.5% center spread. The spread modulation rate is fixed at approximately 31.5 kHz.
The following parameters must be known to properly set up spread spectrum:
Use the equations in the appropriate section below to set up the desired spread spectrum profile. Register descriptions are given at the end.
For down spread, four spread spectrum parameters need to be written: SSUDP[11:0], SSDN_P1[11:0], SSDN_P2[14:0], and SSDN_P3[14:0].
For center spread, seven spread spectrum parameters need to be written: SSUDP[11:0], SSDN_P1[11:0], SSDN_P2[14:0], SSDN_P3[14:0], SSUP_P1[11:0], SSUP_P2[14:0], and SSUP_P3[14:0].
When using the CML driver, no external bias resistors to ground or Vtt should be connected.The CML driver can be used anytime a large swing AC coupled output is needed. The CML driver is individually available for all 4 differential outputs.
The Si5338 CML output driver can be used as long as the following conditions are met
1.Both pins of the differential output pair are AC coupled to the load
2.The load at the receiver is effectively 100 ohms differential
3.The Si5338 PLL is not bypassed
4.The VDDOx supply voltageis 3.3V or 2.5V
Per the current Si5338 datasheet, theCML driver has the same output voltage swing as the LVPECL driver.
1.Max Vsepp = .95 V
2.Min Vsepp = .55 V
3.Typ Vsepp = .8 V
In order to set the CML output driver mode, see the following information from AN411 that has been updated to include the CML mode.
What, if any, are the Si5350/51 power-up sequencing requirements for VDD/VDDO? What if I can't meet it?
If output-to-output phase skew is a concern, then VDDOx should come up either before or at the same time as VDD. Otherwise, power-supply sequencing is not required.
If output-to-output phase skew is improtant, and the above sequence can't be met, then a PLLA_RST and PLLB_RST must be performed by writing a 1 to reg177, bits 5 and 7 respectively. Note that the Si5351 (I2C-controlled version) is required to perform PLL reset. This is not possible with the Si5350. With the Si5350, the sequence must be met if output skew is important to the application.
Why does ClockBuilder Desktop not allow the user to select the output clock pinout?
ClockBuilder Desktop has an algorithm that determines the pinout for best jitter performance based on an individual frequency plan. Single-ended signals on high density PCBs have a higher tendency to inject noise on or pick up noise from adjacent signals, especially if the layout is not optimal. This in turn can degrade jitter performance of a clock signal. This negative effect can usually be minimized with proper layout. However, to make layout easier for the customer, we have included an algorithm for output frequency to pinout mapping on ClockBuilder Desktop. This algorithm attempts to physically separate frequencies that have a higher tendency to talk to one another.
If you feel you have optimized your PCB layout and would like to select the pinout, please take a look at the Knowledge Base article titled 'Modifying Output Frequency on the Fly'.
How can one estimate RMS cycle to cycle jitter from RMS period jitter?
Provided a basic assumption applies, RMS cycle to cycle jitter can be estimated from RMS period jitter as follows:
Jcc (RMS) = sqrt(3) * Jper (RMS)
The basic assumption is that the oscillator or clock output's period distribution is Gaussian or “Normal”, and that the absolute jitter of the clock edges is uncorrelated.The sqrt(3) factor arises from the definitions of period jitter and cycle to cycle jitter in terms of the timing jitter of each clock edge versus a reference clock.
Please see the example file, Si570 100MHz 3V3 LVPECL Scope Screen Cap Diff 1M period histogram annotated.png, attached to this KB entry. Here are a few items noted and called out on the screen capture.
1.The period distribution after 1 million cycles appears Gaussian and comes close to meeting the 68-95-99.7 % rule for standard deviations.
2.The measured RMS period jitter is the standard deviation of the period jitter distribution or about 1.17 ps. We therefore estimate the RMS cycle to cycle jitter as sqrt(3) * 1.17 ps or 2.03 ps.
4.The actual measured cycle to cycle jitter is 2.05 ps which is reasonably close to the estimate.
I am using the Si51x with runts suppressed and with the STOP HiZ option enabled. When I enable the part with this option a small voltage blip appears in the output before normal clock output appears. Why does this occur?
Runt suppression was designed to work with stopping the clock to a known state i.e. high/low. The option to stop to high-Z is intended to work in the mode where runts are NOT suppressed, therefore the mode where runts are suppressed with the outputs stopped to HiZ is not a mode that the part was designed to support. Runts will be suppressed when the device is disabled, however.
The reason the blip is occurring is that internal supplies of the output driver are coming alive while the output driver is being put in a known state.
Interfacing Si5350/51 Clock Outputs to HCSL, LVDS, and LVPECL Receivers
The Si5350/51 clock outputs can emulate some of the most common differential I/O interface standards. This article details the steps required to interface the Si5350/51 outputs to HCSL, LVDS, and LVPECL receivers.
To generate a differential signal, two clock outputs of the same frequency must be used. In addition, one clock must be inverted, 180° out of phase, with respect to the other. Note that by default, all clock outputs are in phase. Invert one of the two output clocks by setting CLKx_INV = 1.
The circuits required to interface to each of the three standards mentioned earlier are given below in Figures 1, 2, and 3.