Configuring the Initial Phase Offset of the Si5351
Each output of the Si5351 can be programmed with an independent initial phase offset. The phase offset parameter is represented as a 2s complement integer, where each LSB represents a phase difference of a quarter of the VCO period, T
vco/4. Use the equation and register descriptions below to determine the register value.
I am using one of the following devices.However, DSPLLsim will not create my desired frequency plan.What are my alternatives?
Si5319, Si5324, Si5326, Si5368
The size of the divisors in the Si5326 family of devices is quite large and the overwhelming majority of input frequency to output frequency ratios are easily accommodated.However, as the multiplication ratios become larger with mutually prime numerator and divisor values, the required diviers values can become too large to fit into their respective registers.
In some applications (e.g. OTN/OTU), there is no need for an exact input to output multiplication ratio.In these instances, DSPLLsim's Inexact Mode will provide alternative frequency plans with simplified multiplication ratios.DSPLLsim will exhaustively search the solution space and provide a set of alternatives that trade off multiplication ratio accuracy against the increased jitter caused by a low f3 (phase detector) value.
Whenever DSPLLsim cannot implement a requested multiplication ratio value, DSPLLsim automatically enters Inexact Mode.The user will be prompted for search parameters and then DSPLLsim will list a number of potential solutions.The user can browse through the solutions and pick one that best fits the requirements. Please note that Inexact Mode is an advanced mode of operation.If assistance is needed, please contact Silicon Labs Applications.
For applications that cannot tolerate even a very small inaccuracy in the multiplication ratio, two cascaded devices should be considered.Different combinations of devices can provide a variety of features, such as jitter attenuation, hitless switching, holdover, etc.
I am using one of the following listed devices and I have an input or output frequency that should not be rounded to the nearest Hz.How can I create my frequency plan?
Si5319, Si5324, Si5325, Si5326, Si5367, Si5368
DSPLLsim rounds both its input and output frequencies to the nearest Hz.There are times when this is not enough accuracy to exactly express an input or output frequency.One example is frequencies that are the result of repeating decimal numbers.However, DSPLLsim's mulitiplication ratios are always the exact ratio of two integers.This means that when you enter frequencies into DSPLLsim, you can round the frequencies to the nearest Hz as long as you have entered the correct multiplication ratio.Put another way, the input and output frequencies may both be slightly rounded, but the multiplication ratio will be correct.As a result, if the input frequency were to be exactly correct, then the output frequency would also be exactly correct.
How to Modify Output Driver Strength of the Si5351.
The Si5351 allows the user the modify the output drive strength of each individual driver. This is a useful tool to have when trying to reduce EMI post-layout. The output drive strength of each individual driver can be modified by the writing one of the following settings to CLKx_IDRV[1:0], where x is 0,1,2...7.
Once I've generated a register map file using ClockBuilder Desktop - Si5351, how do I program these register values into the Si5351?
ClockBuilder Desktop allows a user to generate RAM configuration files to program the Si5351 with custom frequency plans via I2C. Once the register map has been generated, use the procedure below to program the device.
1. Disable all outputs. reg3 = 0xFF 2. Write reg187 = 0xC0 3. Power down all output drivers reg 16 = 0x80* reg 17 = 0x80* reg 18 = 0x80* reg 19 = 0x80* reg 20 = 0x80* reg 21 = 0x80* reg 22 = 0x80* reg 23 = 0x80* * If using the Si5351C with no crystal present on XA/XB, set reg16-23 = 0x84. 4. Set interrupt maks register (see Register 2 description in datasheet) 5. If needed, set crystal load capacitance, XTAL_CL in reg183[7:6]. See datasheet for register description. 6. Write registers 15-92 and 149-170 using the contents of register map generated by ClockBuilder Desktop. 7. Apply PLL A and PLL B soft reset. reg177 = 0xAC 8. Enable outputs with OEB control in register 3.
The following example illustrates how to modify an Si5351 output frequency on-the-fly via I2C.
1. Program the device using a register map file generated by ClockBuilder Desktop (see KB article #311595 – Programming the Si5351 via I2C for details). Note that the register map file contains comments detailing the frequency plan. These will be useful in the following steps. 2. Take an example frequency plan below, where CLK0 must be modified on-the-fly to a new frequency of 24MHz.
PLL A Input Frequency (MHz) = 27.000000000 VCO Frequency (MHz) = 756.000000000 Feedback Divider = 28 SSC disabled
PLL B Input Frequency (MHz) = 27.000000000 VCO Frequency (MHz) = 786.432000000 Feedback Divider = 29 143/1125
3. In this example, note that the PLL source for CLK0 is PLLB, 786.432MHz. This requires a Multisynth0 Divider ratio of 32 + 96/125. 4. Calculate the new Multisynth0 parameters P1, P2, P3 using the equations below, where a = 32, b = 96, and c = 125.
Divider represented as a +b/c
MSx_P1 = 128 x a + Floor (128 * b/c ) - 512
MSx_P2 = 128 x b – c x Floor ( 128 *b/c ) MSx_P3 = c
a. MS0_P1 = 0xE62 (3682 decimal) b. MS0_P2 = 0x26 c. MS0_P3 = 0x7D 5. Write the new parameters.1,2,3
1. Note that the Multisynth dividers are updated when the P2 LSB is written. In order to ensure no intermediate output frequency during the register writes, P2 LSB must be the last byte written. 2. Valid divider values for Multisynth 0-5 are 6, 8, or any fractional value between 8 and 2050 + 0/1. Multisynth 6 and 7 divider values can only be even integers between 6 and 254 inclusive. All other values are invalid. To obtain a lower frequencies, R dividers must be used. 3. See register descriptions below.
What is the recommend termination for LVDS inputs to the Si533x devices?
The datasheet recommends that the 100-Ohm termination resistor be closest to the input pins, but the LVDS input section of AN408 shows the 100-Ohm resistors followed by AC-coupling capacitors. Which is correct?
Some drivers have a common-mode balance issue when AC-coupled to the receiver termination resulting in duty-cycle distortion. To remedy this issue the 100-Ohm termination can be DC-coupled to the driver. Silicon Labs timing devices do not have this issue. If the driving device is another Silicon Labs device, either location is valid and a circuit similar to Fig 16b in AN408 may be used.
What Timing software is compatible with Windows 7? Are there any installation issues?
Timing Software - ClockBuilder Desktop 4.0 for the Si5338/56/51 including the driver is compatible with Windows 7 32-bit. It may not run on a 64-bit computer. - DSPLLsim for the Precision Clocks like Si5324/26/68 including the driver is compatible with Windows 7 32-bit and 64-bit. - Si537x DSPLLsim including the driver is compatible with Windows 7 32- and 64-bit. - Programmable Oscillator Software 2.0 and 3.x for the Si514/70/71/98/99 are compatible with Windows 7 32-bit only. - Si5040 EVB Software will only run on 32-bit systems. NOTE: You will need administrative priveleges to run any of this software on your target computer.
.NET Framework See the installation instructions for each software package to determine which .NET Framework should be run for each program. The Timing software is transitioning from .NET Framework 1.1 to .NET Framework 4.0. Most new computers have .NET Framework 4.0 installed already. Check with your system administrator for more details. EVB Driver Installation for 64-bit Windows 7 The drivers for the software are usually installed after the main software installation wizard runs. If this method does not work on Windows 7 64-bit the drivers will need to be installed manually. To install the drivers correctly:
1.Disconnect the EVB from the computer.
2.Navigate to the EVB Driver directory that came with the installation files for the desired software.
3.Right-click on the exe file and selection “Run as administrator” to start the installer manually.
4.The default installation directory is acceptable or it can be changed.
The Si5330 buffer datasheet specs a minimum input frequency of 5MHz, but I need to operate the device below this point. Can I safely operate the part at a frequency of less than 5MHz?
The differential input Si5330 buffers (Si5330A, B, C, G, H, and J) can operate well into the tens of kHz region, assuming the input capacitors are large enough. However, LOS functionality is not guaranteed below 5MHz.
The single-ended Si5330 buffers (variants F, K, L, and M) are AC-coupled inside the part and must be limited to frequencies greater than or equal to 5MHz as specified in the datasheet.
If a user needs to fanout a single-ended clock source of less than 5MHz, a differential input buffer can be used instead. Keep in mind that the differential input pins of the Si5330 must not exceed 1.3V. Use the circuit shown below to apply a CMOS level signal to the differential input pins of the Si5330, pins 1 and 2. Note that the AC-coupling capacitors must be large enough to prevent distortion of the input signal. A general rule of thumb would be to use a large enough cap such that its impedance, |1/jwC|, is less than a few ohms.
I generated a register map file using ClockBuilder Desktop, but pin-controlled Frequency and/or Phase INC/DEC is not functioning as expected.
ClockBuilder Desktop sets up Frequency and Phase INC/DEC to be controlled via I2C.
To enable pin-controled frequency inc/dec, set reg52[6:5] = 01b. Note that pin-controlled frequency inc/dec is only available on CLK0.
To enable pin-controlled phase inc/dec, set reg52[1:0] = 01b, reg63[1:0] = 01b, reg74[1:0] = 01b, and reg85[1:0] = 01b for CLK0, 1, 2, and 3 respectively. Please refer to Si5338 datasheet for more detailed register descriptions.
I'd like to evaluate LVPECL format clocks on the Si5338 EVB, but I'm not sure if the termination resistors are present on the board.
Before beginning, please refer to the Si5338-EVB user guide for the EVB schematics and AN408 for the LVPECL output termination guidelines.
To evaluate LVPECL signals on the Si5338 EVB, a few components must be soldered down on the board. Let's take the example of setting up 2.5V LVPECL on CLK0. Note that CLK0 has R85, R121/R122, R1/R4, R2/R5, R3/R6, C4/C7, and C15/C17 attached to the nets of interest. The EVB comes with only R121/R122 and C15/C17 installed. This allows support of all output types except LVPECL.
Let's take an example the Si5338 CLK0 AC-coupled to an LVPECL receiver (see AN408). This requires a bias resistor of 130 or 200 Ohms to ground on each of the output lines depending on driver VDDO.
·For 3.3V LVPECL (AC-coupled)
oPlace R1 and R4
oC4, C7 = 0-Ohm resistors
·For 2.5V LVPECL (AC-coupled)
oR1, R4 = 200 Ohms
oC4, C7 = 0 Ohm resistors
The LVPECL output may also be DC-coupled to an LVPECL receiver. To DC-couple the CLK0 output, make the component changes below.Note that R2, R3, R5, and R6 depend on VDDO.
·C15, C17 = 0 Ohm resistors
·R1, R4 = 50 Ohms
·Place C4 and C7
·R2 and R3 (and similarly R5 and R6) must be selected to give a termination voltage of VTT = VDDO – 2 V.
For LVPECL termination on CLK1, 2, and 3 please follow the guidelines above and refer to the Si5338-EVB schematics as needed.
The center ground pad on the Si533x devices must be properly connected to a solid ground plane in order for 1. The datasheet specified output jitter specifications to be met. 2. The heat from the device to be properly dissipated to the ground plane.
Connect the center ground pad to a solid ground plane with no less than five vias. These 5 vias should have a length of no more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distanceto the ground plane is allowed if more vias are used to keep the inductance from increasing.
Why does the Core VDD entry in the NVM files or register map text files saved from ClockBuilder Desktop have 0.0V? Is this a problem for the software or my custom device?
The Core VDD entry in the NVM file saved from ClockBuilder Desktop is not used for custom device orders or field programming. This value is ignored.
If the value is 0.0V, that means the EVB was not connected to the software when the file was saved. Otherwise it will show the VDD that the device on the EVB was using when the file was saved, like 3.3V, 2.5V or 1.8V. There is no register bit that controls VDD in the Si5338/56; the device does not need to be told what VDD to use.
Silicon Laboratories reserves the right to change this usage.
ClockBuilder Desktop software does not save floating point numbers correctly in European Windows operating systems. So when the NVM file is used in the Field Programmer program, the version number is not parsed correctly since it requires a period, when the NVM file has a comma. Also, when the file is sent back to Silicon Laboratories for custom devices, the file will need to be modified to use periods.
The ClockBuilder Desktop and Field Programmer software need to be updated to handle saving and parsing of floating point numbers correctly in the NVM files, regardless of the operating system location.
Please note that ClockBuilder Desktop can read the NVM files correctly, since it does not need some of the information in the header.
Until this bug is fixed, change the following entries to use the period instead of the comma: - '#Software version' - '#VCO Frequency (GHz)'
A software version number like 2,7 should become 2.7
A VCO Frequency like 2,500000 should become 2.500000
Do this when using the Field Programmer and before the NVM file is sent to Silicon Laboratories when ordering a custom device. ClockBuilder Desktop can parse the file successfully. Do not modify any other entries in the NVM file.
Integer-related output clocks are phase aligned on the falling edge. They need to be aligned on the rising edge.
The Si5338/34/55/56 can phase align the integer-related outputs on the rising or falling edge. By default, the alignment is done on the falling edge. To align these outputs on the rising edge, the clocks of interest must be inverted by setting register bits DRVx_INV[1:0] = 11b.
DRV0_INV[1:0] ==> Reg36[4:3] DRV1_INV[1:0] ==> Reg37[4:3] DRV2_INV[1:0] ==> Reg38[4:3] DRV3_INV[1:0] ==> Reg39[4:3 For single-ended clock outputs, individual outputs on a given bank can be inverted by writing DRVx_INV[1:0] according to the settings below. 0: Both outputs are in phase 1: CLK3A inverted 2: CLK3B inverted 3: CLK3A/B inverted and in phase
The Si500 is a silicon oscillator only. There is no external variable resistance resonator such as a crystal which is assembled with or attached to this unit. There is only an on-chip LC tank oscillator which is verified to start up and operate as specified in production test. The oscillation margin for this LC tank oscillator is about 5X typical, 3X worst case.
<Oscillation margin refers to the ratio of the magnitude of the oscillator circuit's negative resistance to the resonator's effective load resistance.>
What is a good way to estimate 10% - 90% rise and fall times from 20% - 80% rise and fall times?
Silicon Labs generally specifies the rise times and fall times of its timing products using 20%-80% threshold levels.This is the convention used by modern standards such as PCI Express.
The question arises as to how to convert from 20% - 80% rise and fall times to their 10% - 90% counterparts. Depending on the assumptions made regarding the waveform, the conversion factors in the literature range from about 1.3x to 1.6x.Cable and connector vendors for example often use a factor of 1.5x.
The largest practical conversion factor is for a single-pole response such as an LVCMOS buffer driving a lumped capacitive load. As derived in the attachment, this ratio can be shown to be roughly tr10-90/tr20-80 = 1.59 or ~1.6.So for example, if a CMOS output buffer is specified to have a nominal 20% - 80% rise time of 1ns, it can be estimated to have a nominal 10% - 90% rise time of 1.6 ns.
Note: If trying to calculate a worst case tr10-90 number based solely on an existing tr20-80 spec or data set, we would suggest adding margin by increasing the conversion factor to 1.7 just to be conservative.