What are the advantages of differential clocks versus single-ended clocks?
Silicon Labs timing device output clocks can typically be ordered or configured to support single-ended CMOS or differential output formats such as CML, LVDS, and LVPECL. A single-ended signal uses a single signal conductor compared to a fixed voltage reference, usually ground. Differential signals use two paired signal conductors whose voltages and currents complement each other.
A clock can be regarded as a binary signal whose duty cycle is nominally 50%. It can be distributed using DC or AC-coupling, in single-ended or differential fashion. So for example, a typical single-ended CMOS clock would be routed as a single microstrip over a GND plane. Likewise, a typical differential output clock would be routed as a complementary pair of microstrip traces over a GND plane. The obvious but relatively minor disadvantage to the differential clock is the requirement to route an additional microstrip.
There are several advantages to using differential signaling. Three of the most important are these:
(1) Differential receivers reject common mode noise due to skew, power supply noise, interference, etc.
(2) Differential signals effectively double the voltage swing at the differential receiver increasing S/N.
See the illustrations in the attached file Differential Swing.docx.
(3) Well balanced and terminated differential transmission lines generate less EMI.
For these reasons, differential output formats are typically selected in high frequency and/or low jitter applications.
There are a number of good online references on this topic such as the following.
· differential signaling articles collection by Howard Johnson, Signal Consulting, Inc, various dates
· Differential Signals by Douglas Brooks, UltraCAD, 2001