What are the concerns when using a system clock faster than 25 MHz?
When using system clock speeds greater than 25 MHz, take the following into consideration:
Set the FLSCL SFR for the appropriate clock speed. The FLSCL register determines the Flash access timing. The Flash memory is rated for 25 MHz access and Flash timing must be adjusted for higher system clock speeds. The prefetch engine on these MCUs enables the code execution to keep up with the higher clock speeds.
The maximum slew rate for inputs and outputs is dependent on the trace capacitance. For pins that are toggling at higher speeds, minimize the trace lengths to reduce the trace capacitance and ensure a higher quality signal.
Certain devices are capable of running at speeds greater than 50 MHz. When running faster than 50 MHz, VDD must be higher than 3.0V. The on-chip VDD monitor threshold for these devices is 2.7V. If VDD monitor functionality is required, use an external VDD monitor.