Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5347 and Si5346 Quad and Dual DSPLL Any-Frequency, Any-Output Jitter Attenuators.
The topics from the Table of Contents are listed below.
PCB Design and Layout Guidance
Where can I find the IBIS model for the Si5347/46?
Where can I find the Si5347/46 schematic footprints and symbols?
Where can I find the package and PCB footprint information?
Do you have layout recommendations I should follow?
Do you have a list of recommended crystals?
I don’t want to use a crystal with the Si5347/46. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device?
Are there any power supply filtering requirements or recommendations?
Is there any specific power supply sequencing requirement?
What serial interfaces does the device support?
How do I properly terminate input and output clocks?
Where can I get detailed material composition information on these devices?
Is the part RoHS compliant?
What is the Moisture Sensitivity Level (MSL) rating for the Si5347/46?
What is the recommend profile for solder reflow process?
Frequency Plan and Clock Design Decisions
What development software/tools do you have available to use with the Si5347/46?
Where can I find ClockBuilder Pro Documentation?
How do I select proper jitter attenuation bandwidth?
Does the device support automatic input clock selection and does it support hitless switching?
Is there a recommended full device programming procedure?
Can I change one output frequency without disturbing other output(s)?
Do I need to write pre-amble/post-amble for Frequency-On-The-Fly?
Should I use Soft_Reset_All or Soft_Reset_DSPLLx for Frequency-On-The-Fly?
Do I need to update any divider if I strobe Soft_Reset_All?
How do I do DCO mode?
Do I have to provide an input clock in DCO mode?
How do I calculate a frequency plan without CBPro?
Does the Si5347/46 support Zero-Delay Buffer operation?