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Si5372/71 FAQ
Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5372 and Si5371 coherent optical clocks.
The topics from the Table of Contents are listed below.
PCB Design and Layout Guidance
Where should I look for schematic design assistance?
Where can I find the IBIS model for the Si5372/71?
Where can I find the Si5372/71 schematic footprints and symbols?
Do you have layout recommendations I should follow?
Do you have a list of recommended crystals?
I don’t want to use a crystal with the Si5372/71. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device? 2
Are there any power supply filtering requirements or recommendations?
Is there any specific power supply sequencing requirement?
What serial interfaces does the device support?
Are there any power supply filtering requirements or recommendations?
How do I properly terminate input and output clocks?
Package Information
Where can I get detailed material composition information on these devices?
Is the part RoHS compliant?
What is the Moisture Sensitivity Level (MSL) rating for the Si5372/71?
What is the recommend profile for solder reflow process?
Frequency Plan and Clock Design Decisions
What is the output frequency range of the Si5372/71?
What development software/tools do you have available to use with the Si5372/71?
How do I select proper jitter attenuation bandwidth?
Does the device support automatic input clock selection and does it support hitless switching?
Is there a recommended full device programming procedure?
Can I change one output frequency without disturbing other output(s)?
What is DCO mode and how to use that?
How much power will my frequency plan draw?
How can I know the performance of my frequency plan if I can’t measure phase noise or jitter?
Dose the Si5372/71 support Zero-Delay Mode?
What is the difference between A grade and J grade?