Please see the attached PDF for the answers to some of the most common Si567 questions.
Please see the attached PDF for the answers to some of the most common Si566 questions.
Please see the attached PDF for the answers to some of the most common Si565 questions.
Please see the attached PDF for the answers to some of the most common Si564 questions.
Please see the attached PDF for the answers to some of the most common Si562 questions.
Please see the attached PDF for the answers to some of the most common Si560 questions.
Please see the attached document for Frequently Asked Questions (FAQ) and their answers regarding the Si5397 and Si5396 Quad and Dual DSPLL Any-Frequency, Any-Output Jitter Attenuators.
The topics from the Table of Contents are listed below.
PCB Design and Layout Guidance
Where can I find the IBIS model for the Si5397/96?
Where can I find the Si5397/96 schematic footprints and symbols?
Where can I find the package and PCB footprint information?
Do you have layout recommendations I should follow?
Do you have a list of recommended crystals?
I don’t want to use a crystal with the Si5397/96. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device?
Are there any power supply filtering requirements or recommendations?
Is there any specific power supply sequencing requirement?
What serial interfaces does the device support?
How do I properly terminate input and output clocks?
Where can I get detailed material composition information on these devices?
Is the part RoHS compliant?
What is the Moisture Sensitivity Level (MSL) rating for the Si5397/96?
What is the recommend profile for solder reflow process?
Frequency Plan and Clock Design Decisions
What development software/tools do you have available to use with the Si5397/96?
Where can I find ClockBuilder Pro Documentation?
How do I select proper jitter attenuation bandwidth?
Does the device support automatic input clock selection and does it support hitless switching?
Is there a recommended full device programming procedure?
Can I change one output frequency without disturbing other output(s)?
Do I need to write pre-amble/post-amble for Frequency-On-The-Fly?
Should I use Soft_Rst_All or Soft_Rst_DSPLLx for Frequency-On-The-Fly?
Do I need to update any divider if I write Soft_Rst_All?
How do I do DCO mode?
Do I have to provide an input clock in DCO mode?
How do I calculate a frequency plan without CBPro?
Does the Si5397/96 support Zero-Delay Buffer operation?
What is the accuracy of the output clocks in relation to the device input clock?
Please refer to AN1051: Si534x/8x Shematic Review Checklist Application Note which can be used as an initial step in evaluating an Si5395/94/92 schematic design. Considering this document before committing to layout will contribute to a successful design.
Please refer to the Si5395/94/92 Reference Manual for crystal and device layout recommendations.
Please refer to the Si5395/94/92 Datasheet for package and footprint information.
Please refer to the Si5395/94/92 Datasheet ordering guide. You can always create a custom OPN with your frequency plan in the NVM via the ClockBuilder Pro Wizard.
Silicon Labs clock and oscillator layout footprints and schematic symbols are available in the online Document Library search tool.
Silicon Labs clocks and oscillators IBIS models are available in the online Document Library search tool.
For optimum jitter performance the reference clock frequency should be in the range of 48-54 MHz. Silicon Labs recommends using a crystal as a low-cost high-performance option for the XA/XB input. However, a crystal oscillator can also be used. A TCXO or OCXO can be used for applications that require tight holdover stability, low wander generation, wander filtering, and/or low bandwidth frequency plans (recommended below 40 Hz).
See AN905: Si534x External References; Optimizing Performance, for a more in-depth discussion on the pros and cons that come with each option for the reference clock. This application note also includes recommended XTAL and XO layout guidelines.
For a list of recommended reference clocks refer to Si534x/8x Jitter Attenuators Recommended Crystals, TCXO and OCXOs Reference Manual.
I2C standard mode (100 kbps) and fast mode (400 kbps) are both supported. The device also supports both 3-wire and 4-wire SPI communication at a rate of up to 20MHz. Both I2C and SPI support I/O voltage of 1.8 V and 3.3 V. Refer to AN926: Reading and Writing Registers with SPI and I2C for Si534x/8x Devices for more information.
It is recommended to use an 0402 1 μF ceramic capacitor on each power supply pin for optimal performance. If the supply voltage is extremely noisy, it might be necessary to use a ferrite bead in series between the supply voltage and the power supply pin.
Refer to the Si5395/94/92 Family Reference Manual for differential and single-ended input and output terminations. Be sure that there are no DC-connected shunt resistors on output pins. This is common for LVPECL but these devices do not support that termination scheme. Be sure to AC couple when necessary per the reference manual recommendations.
Please refer to the Environmental Data Part Number search on the website for this information.
Yes. Please refer to the Environmental Data Part Number search on the website for the certificate of compliance.
These parts are shipped MSL 2.
The recommended reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
The latest versions of ClockBuilder Pro, ClockBuilder Pro Project File Inspector, and other software development tools are available on the Silicon Labs website at http://www.silabs.com/products/development-tools/software/clock.
See the “CBPro Overview” and “CBPro Tools & Support for In-System Programming” on the ClockBuilder Pro Wizard home screen. The latter includes walkthroughs of frequency-on-the-fly and full/partial configuration programming scenarios
Yes. In some cases, the full procedure may not be needed in some cases, but the following is a general procedure recommended for most cases. The user has the option to include these register writes with a CBPro register export.
Select the “Standard” input buffer for AC-coupled inputs that have a nominal 50% duty cycle. The “Pulsed CMOS” input buffer allows pulse-based inputs, such as frame-sync and other synchronization signals, having a duty cycle much less than 50%. These pulsed CMOS signals should be DC coupled.
Yes, refer to Si5395/94/92 Family Reference Manual
This is a highly system-specific decision, requiring a careful balance and understanding of jitter attenuation v. jitter transfer. One place to start is to read the PLL Characteristics section of AN687: A Primer on Jitter, Jitter Measurement and Phase-Locked Loops.
Yes, as long as only the N divider is being altered as this will not cause the VCO frequency to change. Please refer to the Si5395/94/92 Family Reference Manual section 4.2 “Dynamic PLL Changes”. ClockBuilder Pro will automatically generate a register difference file by typing “Alt+D” before making a change with the CBPro Wizard. This tool can be very helpful for determining if the desired change can be done without affecting the other outputs (glitches).
One can reduce harmonic crosstalk in the integration band by separating output clocks that are within 20 MHz of each other. Also, take into consideration harmonic relationships. However, note that this can be ignored when the clocks are integer multiples of one another. Separate clocks with an unused output driver and/or group them together to reduce crosstalk. Designers are encouraged to use the “Clock Placement Wizard” on the “Define Output Frequencies” tab of CBPro which automatically optimizes clock placement.
When possible, select differential output formats. Differential outputs produce balanced, complimentary signals that inherently generate less common mode noise, reducing EMI. As an added benefit, differential outputs generally consume less power. This is due to the fact that CMOS output buffers swing rail-to-rail and are not balanced, making them prime crosstalk aggressors.
In applications where CMOS is needed, keep CMOS output clocks away from outputs that require low jitter and select the “complimentary” output format (instead of “in-phase”) to help balance out the signal. See “AN862: Optimizing Jitter Performance in Next Generation Internet Infrastructure Systems” for more information.
CBPro estimates the typical power on each supply independently and estimates the operating die temperature. Using the ‘Regulators’ tab of the associated CBPro EVB GUI, the real-time power can be measured under any conditions and compared with the estimate.
A phase noise measurement request can be submitted for a frequency plan by clicking the “request a phase noise report” link in the lower left corner of the CBPro ‘Dashboard’ page. Silicon Labs will take the measurements and get results back to you, usually within a few days.
Yes, the Si5395/94/92 supports Zero-Delay Mode (ZDM) to minimize input-to-output clock delay. Please refer to the Si5395/94/92 Family Reference Manualfor more information on Zero-Delay Mode.
Please refer to the Si5395/94/92 Family Reference Manual for the full register map and register descriptions.
Please double check that you have configured the device and host properly for I2C, SPI 4-Wire or SPI 3-Wire. Please refer to section 9 “Serial Interface” of the Si5395/94/92 Family Reference Manual for the host device connectivity configurations.
Yes the Si5395/94/92 jitter attenuators are ideally suited for generating very low jitter clocks for SerDes devices. Refer to AN1151: Using the Si539x in 56G SerDes Applications
The PLL inherently locks the input frequency to the output frequency minimizing the frequency and phase error to zero.
56G/112G SerDes applications that requires the following features
Anyone who does not need the above improvements can continue to use the Si534x
The P grade is calibrated for 56G SerDes 156.25M and 312.5Mhz outputs. BUT there are restrictions on the inputs and the crystal and what outputs can be selected. A/B/C/D has more flexibility but slightly higher jitter. For more information about the P grade restrictions refer to the reference manual.
NO. P grade device must use 48MHz crystal with restrictions on accuracy etc. See reference manual for details.
The architecture of Si5396/97 does not support this calibration tuning to enhance the extra performance.
Typical 56G serdes will have either 156.25M or 312.5MHz. But they will also need additional frequencies like 125/100/50/25. It is important to ask about ALL these frequencies because only Si539x can support all of these at the same time and deliver low jitter <100fs on all supported SerDes outputs