AC Coupling, Capacitive Reactance and Clock Signals

Clock signals are usually AC coupled because AC coupling eliminates needing to consider the DC common mode voltages of the driver and receiver.  The vast majority of clock signals have a constant 50% duty cycle, which makes AC coupling easy and straightforward.  However, when selecting a value  for the AC coupling cap, the frequency of the clock and the impedance being driven need to be taken into consideration.

For a cap value of C, the capacitive reactance Cx at a clock frequency of F is 1 / (2 * pi * F * C).  For a 0.1 uF cap, the capacitve reactance at 10 MHz is

1 / (2 * pi * 10 MHz * 0.1 uF) = ~0.16 ohms

Looking at the attached termination schematic, Cx should be small compared to the termination resistance and the transmission line impedance of 50 ohms.  A reasonable “rule of thumb” is to be sure that Cx < 5 ohms, which  is 10% of 50 ohms.

If F were 1 MHz, Cx for a 0.1 uF cap would be 1.6 ohms, which would be OK.

However, if F were 100 kHz Cx would be 16 ohms, which is above 5 ohms and will be a problem unless the value of C is increased.  The specific problem is that the input clock will be attenuated by the ratio of Cx to 100 ohms, which will reduce the pk-pk swing of the input clock.

A note of caution:  The above discussion refers only to the fundamental of the clock input.  Since the clock input is assumed to be a square wave, there will be considerable spectral content at the odd harmonics.  Because these harmonics are all higher in frequency, they will be attenuated more than the fundamental.  With severely attenuated odd harmonics, the rise/fall time of the clock signal will be significantly reduced, which will cause an increase in jitter at the input of the receiver.  Unless the receiver provides jitter attenuation, the AC coupling cap should have an even lower Cx value at the frequency of operation.  It is for this reason that the clock outputs are more sensitive to high Cx values than the clock inputs of a jitter attenuator.

Here are two phase noise plots taken with an 8 kHz and a 80 MHz clock input.  I picked 80 MHz as the high speed clock input so that everything else would be the same including the VCO frequency, etc. so that it is a true apples-to-apples comparison.  The attached project files indicate that the two Fpfd values are the min and the max:  8 kHz and 2 MHz.

As you can see, the 12 kHz to 20 MHz jitter values are similar, though the 8 kHz case has some additional spurs. Some of the spurs are outside of the integration band so that they don’t impact the RMS jitter value.  Note that the 8 kHz close-in phase noise is not as good.
 

Please see the attached PDF for the answers to the following questions: 

1      Are the Si515 and Si516 pin-outs, PCB land patterns, and package dimensions compatible with industry standards?

2      What is the material composition of the pins?

3      What is the MSL (Moisture Sensitivity Level) of the ceramic packages?

4      What is the MSL (Moisture Sensitivity Level) of the 2.5x3.2mm package?

5      Are the CLCC packages hermetically sealed?

6      What about RoHS, REACH or other materials related compliance information?

7      Are any flame retardants (Halogen compounds) used in the Si515 or Si516 packages?

8      How much do the Si515 and Si516 oscillators weigh?

9      Are the oscillator products available in Tape & Reel?

10   What is the maximum operating junction temperature for the Si515 and Si516 devices?

11   What are ΘJA and ΘJC for the Si515 and the Si516?

12   What is the Coefficient of Thermal Expansion (CTE) in the plane of the PWB (x and y) for the 2.5x3.2mm package?

13   What is the typical temperature rise of the Si515 and Si516?

14   Are the devices compatible with both leaded and “lead-free” assembly processes?

15   What are the maximum reflow temperatures and profiles recommended for “lead-free” and “leaded” solder reflow processes?

16   Where is the FIT information for the Si515 and Si516?

17   What are the qualification test requirements for Silicon Laboratories’ lead-free, RoHS-compliant, CLCC package technology?

18   Is the FS pin on a Si515 or Si516 internally pulled up or pulled down?

19   What is Absolute Pull Range (APR)?

20   Why is there no Min APR listed for 2.5v or 1.8v for certain Kv values?

Please see the attached PDF for the answers to the following questions: 

1      Are the Si510, Si511, Si512, or Si513 pin-outs, PCB land patterns, and package dimensions compatible with industry standards?

2      What is the material composition of the pins?

3      What is the MSL (Moisture Sensitivity Level) of the ceramic packages?

4      What is the MSL (Moisture Sensitivity Level) of the 2.5x3.2mm package?

5      Are the CLCC packages hermetically sealed?

6      What about RoHS, REACH or other materials related compliance information?

7      Are any flame retardants (Halogen compounds) used in the Si510, Si511, Si512, and Si513 package?

8      How much do the Si510, Si511, Si512, and Si513 oscillators weigh?

9      Are the oscillator products available in Tape & Reel?

10   What is the maximum operating junction temperature for the Si510, Si511, Si512, and Si513?

11   What are ΘJA and ΘJC for the Si510, Si511, Si512, and Si513?

12   What is the Coefficient of Thermal Expansion (CTE) in the plane of the PWB (x and y) for the 2.5x3.2mm package?

13   What is the typical temperature rise of the Si510, Si511, Si512, or Si513?

14   Are the devices compatible with both leaded and “lead-free” assembly processes?

15   What are the maximum reflow temperatures and profiles recommended for “lead-free” and “leaded” solder reflow processes?

16   Where is the FIT information for the Si510, Si511, Si512, and Si513?

17   What are the qualification test requirements for Silicon Laboratories’ lead-free, RoHS-compliant, CLCC package technology?

18   Is the FS pin on a Si510, Si511, Si512, or Si513 internally pulled up or pulled down?

Please see the attached PDF for the answers to the following questions:

1      Is the Si514 pin-out, PCB land pattern, and package dimensions compatible with industry standards?

2      What is the material composition of the pins?

3      What is the MSL (Moisture Sensitivity Level) of the ceramic packages?

4      What is the MSL (Moisture Sensitivity Level) of the 2.5x3.2mm package?

5      Are the CLCC packages hermetically sealed?

6      What about RoHS, REACH or other materials related compliance information?

7      Are any flame retardants (Halogen compounds) used in the Si514 package?

8      How much does the Si514 oscillators weigh?

9      Are the oscillator products available in Tape & Reel?

10   What is the maximum operating junction temperature for the Si514?

11   What is the ΘJA and ΘJC for the Si514?

12   What is the Coefficient of Thermal Expansion (CTE) in the plane of the PWB (x and y) for the 2.5x3.2mm package?

13   What is the typical temperature rise of the Si514?

14   Are the devices compatible with both leaded and “lead-free” assembly processes?

15   What are the maximum reflow temperatures and profiles recommended for “lead-free” and “leaded” solder reflow processes?

16   Where is the FIT information for the Si514?

17   What are the qualification test requirements for Silicon Laboratories’ lead-free, RoHS-compliant, CLCC package technology?

18   What is the I2C address of my Si514?

19   Is the I2C Bus working correctly?

Please see the attached PDF for the answers to some of the most common Si595, Si596, and Si597 questions. 

Please see the attached PDF for the answers to some of the most common Si598 and Si599 questions.

Please see the attached PDF for the answers to some of the most common Si55x Questions. 

Please see the attached PDF for the answers to some of the most common Si53x questions.