See the attached file.
IO_VDD_SEL bit setting used in the Si534x/8x/9x Customer Evaluation Boards:
The Si539x/8x/4x jitter attenuator timing devices have a power setting IO_VDD_SEL which controls the voltage level to various GPIO pins within the timing chip including the communications pins and status control pins. Please verify with the datasheet for exact pins affected by this power setting.
For systems using a +1.8V host, it is optimal to set IO_VDD_SEL = 0 and all external pullups should be connected to +1.8V. Note that the device GPIO pins are always 3.3V safe regardless of the IO_VDD_SEL setting. The internal GPIO pull-up voltage changes with IO_VDD_SEL (0x0943). It is +1.8V when 0 and +3.3V when 1. In addition to the internal pullup/pulldown, the logic thresholds for the GPIOs are also adjusted by IO_VDD_SEL to give optimum noise immunity at each supply voltage.
The customer evaluation boards (CEVBs) have external pull-ups for these pins set to +3.3V regardless of the IO_VDD_SEL device setting. This is done on the CEVBs because the DUT is always communicating at +3.3V with the MCU for both for SPI/IIC and GPIO inputs and outputs. The DUT should be set to use IO_VDD_SEL = 1, but it will still work when this value is 0. Note that measuring the voltage will always read +3.3V regardless of IO_VDD_SEL. The CEVB MCU has weak software pull ups on the GPIO inputs. Measuring without the CEVB hardware pullups, but with MCU still connected, reads +2.0V when IO_VDD_SEL = 0. Disconnecting the MCU jumper resistor as well as the external pullups gives the correct device value of +1.8V when IO_VDD_SEL = 0. This
Please refer to the datasheet to ensure which pins are affected by the IO_VDD_SEL setting and follow all the datasheet and reference manual recommendations.
Si538x/4x/9x General Troubleshooting Guidelines: I’ve set up my timing chip but I do not see an output
1. Make sure there is power to each of the VDDOs. If using a Silicon Labs EVB this means you can go to the EVB GUI of CBPro to the Regulators Tab and make sure the regulators are all turned on. Or you can turn them on and keep them always on using the jumper pins on the EVB located near each of the outputs. See KB Article about EVB Outputs for the Si534x/9x/8x https://www.silabs.com/community/timing/knowledge-base.entry.html/2018/11/08/si534x_9x_8x_evbout-HMKe
2. Check the OEb pin on the chip. The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be disabled. When the pin is not driven, the device defaults to all outputs on. The OEb pins have an internal pull down. For the Si5397 and Si5347 devices when using the OE1b it is recommended to use an external pull down to ensure the outputs are on, or a pull up to ensure they are off and not leave this pin floating. The OE0b pin has an internal pull down, but this OE1b pin does not in this case only. Outputs in the enabled state can be individually disabled through register control. Please NOTE: If the OEb pin is high, then register control is disabled, and all outputs will be disabled.
3. Check the OUTx_PDN Registers and make sure they are NOT powered down. Also check OUT_PDN_ALL, and PDN. These are all documented in the reference manuals for the specific parts.
4. Check the Output Enable Registers (OUTx_OE). Verify that the outputs are enabled . Also make sure OUTALL_DISABLE_LOW is set high, ensuring all outputs are not disabled. This is a register to disable all outputs by clearing this bit.
5. Connect to CBPro and read the EVB GUI status registers? An output may not appear if something is wrong with the XAXB input. Verify there is no XAXB Error. If there is an Error, check the input going to the XAXB. This may be what is causing the issue.
6. Is the chip programmed correctly? Verify some registers that were written from the frequency plan on different pages to make sure there wasn’t an issue with programming the chip. See AN926 for detailed examples on how to program these devices. It is possible the device was not programmed correctly which is causing the problem. https://www.silabs.com/documents/public/application-notes/an926-reading-writing-registers-spi-i2c.pdf
Si534x/9x/8x General Troubleshooting Guidelines: My timing device does not lock
This is a common question for jitter attenuator timing devices. One thinks the device is configured properly. The chip was programmed for the correct frequency plan file/ register set and it should just lock and work, but there is indication that the device is not locked either from the LOL alarm status or because downstream systems are failing. The following are some helpful troubleshooting steps to consider particularly for the Si534x/9x/8x jitter attenuator devices.
1. Verify the hardware is set up correctly: Do a quick schematic review, following the checklist: https://www.silabs.com/documents/public/application-notes/AN1051-Si534x-8x-Schematic_Review-Checklist.pdf
Make sure the expected inputs are on, measured and are the correct frequency. Make sure to use proper terminations and input levels and rise time considerations. Make sure the correct source is used on the XAXB input and programmed accordingly to the correct expected frequency. Make sure the correct communications are enabled (either I2C/SPI). Also double check that the frequency plan matches the hardware setup, such that programmed input frequencies, and XAXB input frequency correctly matches the hardware.
2. Verify the alarms: What alarms are active when the device does not lock? Please review the appropriate reference manual to find the register values for these alarms and check the status.
LOL: This is the indicator that the device is not locked. This is the issue you are debugging. This should be set showing the device is not locked. Let’s find out why!
SYSINCAL: This shows at start up the device is stuck in calibration. This indicates that device is busy in the calibration routine. This might be that the chip is improperly set up, programmed incorrectly or has the wrong xaxb input frequency if this alarm remains set.
LOSXAXB: This shows that the PLL is not seeing the XAXB input signal. Is the XTAL soldered properly to the board to the XAXB input pins? If using an XO is it turned on, connected and has the proper input constraints per the datasheet?
XAXB_ERR: There is a problem locking to the XAXB input. This indicates that the part may be programmed to the wrong frequency or the XAXB input may be different from what you were expecting, or there is a violation of the input specifications. Verify all input datasheet specs, the programmed frequency and measure the frequency going into XAXB.
OOF: This flag indicates that the input is outside the set threshold frequency range. You can widen the OOF threshold limits to see how far off the input signal is.
LOS: This is the loss of signal flag indicating that the input does not see an input signal. Please check that the input is connected to the expected input and all datasheet parameters are met.
3. Which input is the device expecting to lock to? Check register IN_ACTV. This is a read only register which give the current selected DSPLL input clock. For the Si5345 this is register 0x0507 as there is only one PLL. For multi PLL devices make sure to verify which PLL the loop is configured to. In multi PLL devices these will be labeled IN_PLLA_ACTV, IN_PLLB_ACTV, IN_PLLC_ACTV, IN_PLLD_ACTV.
4. Verify the input control settings: If pin controlled, then check the pin settings. If register controlled then check IN_SEL. If using a device with Zero Delay mode enabled verify with the reference manual for the input selection details. When this function is enabled the inputs can be register controlled with ZDM_IN_SEL.
5. Verify the device was programmed correctly: The Si534/8x devices have 2-byte wide register addresses but the device is only 1-byte programmable. The upper byte of the address is stored as the PAGE register which is always address 0x01. This often confuses customers. Please review AN926 for details on reading and writing registers with SPI and I2C. This document contains examples on how to properly communicate to the part. https://www.silabs.com/documents/public/application-notes/an926-reading-writing-registers-spi-i2c.pdf . It is also good to do a few sanity checks that the device was programmed correctly by reading back several of the registers written to the device, on different pages.
I have one of the Silicon Labs Timing Jitter Attenuator/Clock Generator Si534x/8x/9x evaluation board boards that uses CBPro and I cannot see an output signal after configuring my plan.
The CBPro software has a configuration wizard to help customers create their frequency plan, informing the customer of all the decisions they need to make to optimize all the settings. CBPro also has an EVB GUI which allows the user to do some debug, control the output regulators and view status alarms while the device is running. If the outputs are not turning on it is most likely that the output voltage regulators are not on. To check this, go to the EVB GUI and click on the Regulators tab and turn on the output regulators. They are operable independently.
One can also control the output regulators from the EVB so the PC is not required to turn on the regulators. There is an Enable jumper that can be installed for each of the outputs. When the jumper is set this enables the output. Then there is another jumper that can be installed to select between 1.8V, 2.5V and 3.3V. Attached is an image of a Si5394 EVB pointing to the output driver jumper area for output 1.
Si538x/4x/9x Devices Hardware Reset Delay with Zero Delay Mode Enabled
There are a few devices such as the Si5345, Si5395, Si5380 that have a Zero Delay Mode feature. When this feature has been enabled the hard reset will cause a longer delay before the device is ready. The question is why does the device behave differently when Zero Delay Mode (ZDM) is enabled?
In ZDM the device takes approximately 750ms before the device ready flag will be ready. This occurs whether the device is reset by pin or by register. When in this mode after a hard reset command is received by the device, it will wait for each active output driver to shut down synchronously. The output driver used for ZDM feedback is forced on at all times and the device waits for a special reset timeout counter to expire before continuing with the usual hard reset operation. This timeout counter is set in the baseline of the device by a silabs only register setting. This timeout cannot be bypassed. It is possible to reduce the value down to 145ms. Contact Silicon Labs for assistance if this shorter time period is required. Otherwise, it is advised to wait the minimum time period of at least 750ms after a hard reset, or if polling is desired one can poll the DEVICE_READY register.