Si534x/7x/8x/9x output normal mode disable state has two choices: Stop High and Stop Low.

1. Stop High means that when the output driver is disabled the plus output will be high and the minus output will be low.

The voltage of the output positive V(Out+) = Vbias + Vpp_se, and the voltage of output negative V(out-) = Vbias - Vpp_se

         2. Stop Low means that when the output driver is disabled the plus output will be low and the minus output will be high.

The voltage of the output positive V(Out+) = Vbias - Vpp_se, and the voltage of output negative V(out-) = Vbias + Vpp_se

There are two ways to control Si5332 output signal enable/disable. One is to configurate register 0xB6 and 0xB7 direclty by I2C. Another is assign GPI to control output with CBPro, but please note that these outputs can't be controled by register 0xB6 and 0xB7 if you have already assigned GPI to control some outputs enable/disable.

Crystal Reliability and Activity Dips

Activity dips can cause disruptions to networking systems and are a regrettable but chronic problem associated with the use of crystals.  An activity dip can occur when there are material imperfections in the quartz.  These impurities in the crystal structure cause modes of resonance (often called spurs) that are small in amplitude and not located at the fundamental, 3rd overtone, 5th overtone, etc. frequencies. 

These resonance modes (or spurs) typically do not cause problems because their amplitude is so much smaller than the amplitude of the fundamental.  However, they can have a very large coefficients of frequency vs. temperature.  The problem occurs when an oscillator is running at the fundamental and the temperature is changing.  In these conditions, the frequency of the spur will be changing much faster than the frequency of the fundamental.  If the spur happens to cross over the fundamental, there can be a disruption in the crystal’s oscillation.  If the temperature is ramping, this disruption will be temporary because the spur will continue to move and will move away from the fundamental.

The root cause of activity dips is the impurities in the crystal material itself and the probably of having a crystal that is prone to his problem will decrease with better control of the crystal material processing.  Crystal manufacturers work very hard to keep the material as clean as possible and therefore the probability of an activity dip is very low.  However, it will never go to zero and activity dips are a perennial problem for equipment manufacturers.

What can be done about activity dips?  There are three alternatives:

1. Ignore them because they are low probability – This makes sense in certain situations.  However, low probability events do occur and because of the nature of the problem, they are likely to occur in the most painful of situations: in the field.  While this might be acceptable for low-cost consumer equipment; but it can become a serious problem for carrier class equipment.
2. Screen equipment for activity dips before sending it into the field – By ramping equipment up and down in temperature while monitoring the system clocks for activity dips, crystals can be effectively screened.
3. For a modest fee, you can buy crystals that have already been screened for activity dips by the crystal manufacturer.

Please note that the embedded crystal versions of the Si537x/8x/9x devices all use solution #3.

For more details on activity dips, see page 57 of the following document:

https://escies.org/download/webDocumentFile?id=62209

Accuracy of Phase Noise Measurements With Frequencies Below 100MHz

To ensure the accuracy of the measurements when taking phase noise plots and making RMS jitter measurements, there are times when the instrument being used to take the plots needs to be examined. In particular, the noise floor of the phase noise analyzer (which is typically the Keysight E5052B) needs to be compared to the phase noise being generated by the DUT (device under test).  The phase noise of the Si534x/8x/9x devices is so low that in certain circumstances, it is lower than the noise floor of the E5052B. 

For a clock that is divided by two by an ideal divider, the phase noise will go down by 6dB.  Accordingly, if a phase noise plot of a 2 GHz signal is compared to a phase noise plot of the same signal divided by two, the two plots will look very similar, except that the 1 GHz plots will be 6dB below the 2 GHz plot. With continued divisions by two, the phase noise will go lower and lower until it eventually runs into the noise floor of the E5052B.  At this point, the phase noise plot cannot go any lower and the measurement “saturates”.  The result will be that the phase noise values will be erroneously reported to be greater than they actually are.  The same will be the case for the RMS jitter value because it is derived from the phase noise data. 

Though this process is somewhat gradual, it has been our experience that phase noise plots for the Si534x/8x/7x/9x devices with plots below 100 MHz in frequency are affected by the noise floor of the instrument, while phase noise plots for clock frequencies above are typically OK.  This is not to say that phase noise plots taken below 100 MHz have no value.  Rather the results need to examined in light of these limitations.

For a more detailed discussion of this (and aliasing of higher frequency components down in frequency), see:

https://www.edn.com/design/analog/4368511/Perfect-timing-performing-clock-division-with-jitter-and-phase-noise-measurements