For CMOS output, usually we need to add series resistor at source end to make sure source end impedance matched since the cap load(impedance unmatched at load end), or the signal integrity will be bad. Please check part's datasheet for specific impedance of CMOS output.

Please refer to below diagram for detail information:

Best Regards,

Xiong Wu

What is output skew?

Output skew is a user defined time delay added to each N-divider, which may be useful to adjust the relative phase of the outputs. Output skew can be categorized into dynamic skew and static skew. Static skew is a change in the output phase that is done once at power up or after a reset. Static skew is used if a known absolute time difference is required from the input to the output. Dynamic skew is a change in the output phase that can be done while the part is still running, and no reset is done.

Which products offer what type of output skew?

Within the Si534x/7x/8x/9x product line, the table below shows the availability of static and dynamic skew for the wired and wireless clocks. If applicable, the resolution of the skew is also given in terms of Fvco, where Fvco is the VCO frequency.

Under high device junction temperatures in the Si534x/7x/9x parts, it is possible that all the output Multisynths (N dividers) may not start at exactly the same time. This effect may be different after each reset or power cycle at high temperatures. For this reason, static skew is not supported on the Si534x/7x/9x products. Dynamic skew would be used after the phase difference of two outputs is measured and a small adjustment is necessary. However, this issue is not present in the Si538x parts. For information on programming dynamic and static skew for the Si538x parts, see AN1165.

For applications that require a known input to output delay, it is recommended to use the Zero Delay Mode feature. If outputs are using the same N divider then they will always start at the same place relative to each other.

*Note that for devices with static skew, the resolution is reduced to 1/Fvco if the N-divider is an integer value.