Please refer to attachement for detail information

People sometimes mix the definitions of Time Interval Error (TIE) jitter and period jitter and easily make a common mistake of calculating TIE jitter but with period jitter formula for a spread spectrum clock (SSC). Let's denote the clock frequency as F, the down spread linear modulation as d, the modulation rate as fm, and then the increase of peak to peak value of period jitter due to spread spectrum is given by: 

PJpp = d/((1-d)F); 
the increase of peak to peak value of TIE jitter due to spread spectrum is given by:
TIEJpp = d/(8fm). 

Take a PCIe SSC as an example: F = 100MHz, d = 0.5% (down spread), fm = 30KHz - 33KHz. It gives a PJpp of 0.05 ns and a TIEJpp of 18.9ns - 20.8ns.

Regarding DDR design, there are some clock such as 33.333333...MHz, 133.333333...MHz and 166.666666...MHz etc. Generally 33.333333MHz, 133.333333MHz and 1666.666666MHz are used to approximate value. This method will introduce more spurs and less accuracy. 

Silicon Labs Multisynth technology can support 100MHz/3, 400MHz/3  and 500M/3 configuration to get exact clock with 0ppm. This configuration can reduce spurs as well.

The recommended termination is shown below.

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedance and drive strengths. A series source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance (Rs = Trace Impedance – Zs). For example, the driver impedance Zs is configured to 38 Ohm, and the trace impedance is 50 Ohm. So the Rs is 12 Ohm.

1. If you change output impedance, please change Rs accordingly.

2. Use of the complementary CMOS for one pair OUTx/OUTxb is recommended to help balance the output current surges during transitions. It will reduce the crosstalk noise for adjacent channel.

3. Generally, the lowest impedance for a given supply voltage is preferable, since it will give the fastest edge rates. The faster edge rate means more crosstalk noise to adjacent channel.  If the jitter performance of adjacent channel is high priority, the higher impedance should be selected to reduce the noise.

These transients can be removed by the following process

1. Set OUT_PDN_ALL = 1 (0x0145 = 1) before any registers of the new plan are written

2. Just before the post amble is written (after all the other writes), set OUT_PDN_ALL = 0 (0x0145 = 0)

No, but after the ADC aligns to the first edge of the SYSREF clock, the SYSREF clock can be turned off. This is performed by setting the OUTx_OE bit = 0 for the output that is driving the SYSREF clock.

The Si5386/82/81 is internally optimized to output the LTE/CPRI frequencies with the lowest possible phase noise (jitter) using a very low noise external 54 MHz XO. For this reason the 5386 can be expected to have lower output phase noise and spurs than a 5345/95 for LTE/CPRI frequencies.

The factors that affect the Si5345 output phase noise are?  

1. Is the 5345/95 using an XO or crystal?
2. What frequency is the XO or crystal?
3. What is the phase noise (jitter) of the XO?
4. What are the non LTE/CPRI output frequencies?
   1. These may affect the CBPro algorithm that configures the Si5345/95 such that the LTE/CPRI output frequencies have higher phase noise or spurs

A differential input into Xa and Xb is more immune to noise pickup than a single ended input into Xa only. A fast slew rate is less effected by noise than a slower slew rate. Since we want the lowest possible output phase noise with the Si538x family of parts, a single ended input to Xa needs to have a faster input slew rate.

An internal clock of about 50 MHz samples the level of the RESETb pin. When several consecutive samples are low, the reset will be started. We recommend a minimum low time of 200 ns for the RESETb pin to be recognized as a low.

The Si5381/82/86 are intended for high performance wireless applications which require ultra low close-in phase noise and have very tight spur masks. To meet these high demands we recommend the customer use one of the 54 MHz XOs listed in table 2.3 of the recommended crystal oscillator (XO) reference manual https://www.silabs.com/documents/public/reference-manuals/si534x-8x-9x-recommended-crystals-rm.pdf. These XOs have a very low close-in phase noise profiles as well as low jitter.

Although the Si5381/82/86 device itself has many LDOs on-chip and very good PSR, XOs most of the time do not. Any power supply noise on the XO greater than the DSPLL BW will be seen at the output of the Si5381/82/86 device. For this reason it is critical to use a low noise LDO to supply power to these oscillators. An example of an ultra low noise LDO can be seen in the Si5386A-E-EVB schematics https://www.silabs.com/products/timing/clocks/wireless-jitter-attenuators/device.si5386a. Typically we recommend LDOs with less than 10 uVrms noise integrated from 10 Hz to 100 kHz.

It is acceptable to use the same LDO to supply power to the other 3.3V supplies on the SI538x device such as VDDA or VDDOx but it is not recommend to use this LDO to supply power to other ICs in your system.