There is some tables to show the I2C data protocol in datasheet. Here is some figures to illustrate the protocol clearly.
1. Block Read
2. Block Write
3. Byte Read
Please be noted that Si53152/4/6/9 all need a valid input clock in order for the I2C interface to work.
CBPro implements the DCO function on a Si5395/94/92/45/44/42 by changing the numerator (Nx_NUM) as this gives a higher resolution than changing the N divider denominator (Nx_DEN). However the DCO function can be implemented by changing the Nx_DEN value and this KB article describes how to do this. Note that when changing the Nx_DEN value instead of the Nx_NUM value the minimum step size will increase by approximately the Nx divider value. This is because the Nx_NUM register is 44 bits and the Nx_DEN register is 32 bits. Changing the Nx_NUM term causes an extremely small non-linearity, which will not be a problem except for very rare applications. Changing the Nx_DEN term does not cause any non-linearity.
The DCO function of Si5395/94/92/45/44/42 devices is implemented by changing the Nx_DEN value in one of two ways:
Here is the procedure to implement a DCO function by changing the Nx_DEN term:
More information about DCO applications for Si5395/94/92/45/44/42 can be found at:
The Si5395/94/92/91/45/44/42/41 parts have a maximum output frequency of 1028 MHz. However, there are a few gaps below 1028 MHz which are not valid output frequencies. Why is this the case?
The output clock frequency is equal to the VCO frequency divided down by an output divider. Below 720 MHz, the output divider is able to operate in either fractional or integer mode. Therefore, any output frequency below 720 MHz can be synthesized. Above 720MHz, however, the output divider must be equal to an even integer value, with an exception made for the odd value of Fvco/Fout = 15. The dual constraints of an even integer divide ratio and a limited VCO tuning range lead to a couple of small gaps in the allowed output frequencies. More specifically, the frequencies from 720 MHz --> 733.334 MHz and 800 MHz --> 825 MHz are not valid output frequencies. The figure below shows a conceptual diagram of the valid and non-valid output frequency ranges. The blue areas show the valid output frequency ranges, and the red areas show the non-valid output frequency ranges.
The above definition of the valid and non-valid output frequency ranges holds true only if one unique frequency from the upper frequency range (720 MHz --> 1028 MHz) exists in the frequency plan. This is because selecting an output frequency from the 720 MHz --> 1028 MHz range fixes the VCO frequency. Therefore, selecting two or more unique output frequencies (noting that they both require integer dividers) from the upper range may present competing requirements for the VCO frequency and hence result in a non-synthesizable frequency plan.
A few examples of valid and non-valid frequency plans are listed below: