Typically, /CS pin of Si534x/8x/9x SPI should be pulled up to be High (logic 1) between each two bytes transfer for reliability. In case of rare alignment issues, setting /CS high will help the SPI logic to recover by reinitializing its state machine. An example timing diagram of issuing the pulse of /CS is shown as below:
An example brief timing diagram of /CS pulse sequences is shown in the below figure. The left sequence is recommended for Si534x/8x/9x SPI; the right one may work to achieve several transfers of more than two bytes while /CS is kept as low. However, it is the responsibility of the user to test sufficiently to ensure SPI communication reliability.
Si5348 have 3 output enable pins, i.e. OE0b, OE1b and OE2b. Those output enable pins can be mapped to control any of the outputs (OUTx) through the configuration steps below:
Step 1: Set 0x0022h = 0 to enable using OExb pins to control the outputs.
Step 2: Set the mask registers below to map the outputs to OExb pins.
OExb mask registers (above) are used to configure the outputs to be under control by OExb pins (logic 1) or not (logic 0), respectively. Note that the same bit of three OExb mask registers should not be set as 0 at the same time otherwise the corresponding output will be disabled no matter OExb pins inputs.
This is following the example mappings from the table above:
Example Out 0, Out 1, Out 2 controlled by OE0b pin.
Write 0x0023h = 0x38h
Write 0x0024h = 0x00h
Example Out3, Out4 and Out5 controlled by OE1b pin.
Write 0x0025h = 0x80h
Write 0x0026h = 0x03h
Example Out 6 controlled by OE2b pin.
Write 0x0027h = 0x00h
Write 0x0028h = 0x08h