The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.

Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.

Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.

*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.

Proper HCSL Termination Networks

Examples of Improper HCSL Termination Networks

In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.

An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.

It is okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled differential input format such as LVDS, LVPECL, or HCSL
• The clock is a DC coupled CMOS clock whose voltage levels are constrained to be within -1.0V and +3.8V.
• The clock is an AC coupled CMOS clock with a peak-to-peak swing <2.0V. Note that this peak-peak swing must take into account any overshoot or undershoot of the CMOS signal

It is not­ okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled CMOS clock with a peak-to-peak swing >2.0V. Note that this peak-to-peak swing must take into account any overshoot or undershoot of the CMOS signal.

Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.