1       Package Information

1.1       Where can I get detailed material composition information on these devices?

1.2       Is the part RoHS compliant?

1.3       What is the Moisture Sensitivity Level (MSL) rating for the Si5388/89?

1.4       What is the recommend profile for solder reflow process?

2       PCB Design and Layout Guidance

2.1       Where can I find the IBIS model for the Si5388/89?

2.2       Do you have a list of recommended crystals?

2.3       I don’t want to use a crystal with the Si5388/89.  Can I use an XO or TCXO as the XA/XB reference instead?  And if so, how do I interface an external oscillator to the device?

3       ITU-T Standards-related questions

3.1       What IEEE 1588 Profiles are included in the current solution

3.2       Does this solution meet ITU G.8262 for SyncE and G.8262.1 for Enhanced SyncE?

4       Evaluation system-related questions

4.1       How do I get a complete evaluation system?

4.2       What software is available for the evaluation system..

4.3       Why is a Xilinx FPGA evaluation board required?

4.4       My Xilinx Carrier Card (ZCU102 or ZCU111) is not passing self-test – what could be wrong?

5       System architecture-related questions

5.1       What system architectures does this solution support?

5.2       What clock configurations does the Si5388/89 solution support?

6       Compliance-related questions

6.1       Is a compliance report available?

6.2       What type of reference clocks can you provide G.8273.2 compliance reports for?

6.3       What class do you support for ITU-T G.8273.2 compliance?

6.4       What ITU-T Recommendations do T-TSC (slave clocks) need to comply with?

7       Device configuration-related questions

7.1       What serial interfaces does the device support?

7.2       Does the Si5388/89 support Zero-Delay Mode?

7.3       Can the application FW and/or device configuration (i.e. Frequency Plan) be modified by the user independently and how is this done?

7.4       Are there any restrictions on which DSPLL can be used for IEEE 1588 synchronization?

7.5       Can I DCO a DSPLL that’s in Holdover/Free Run?

7.6       My reference PLL is indicating that’s it’s not in lock.  I’m providing a good XTAL and Reference clock – what could cause this?

7.7       Why can’t I see the Si5388/89 in the listing of Network Synchronizers in CBPro?

8       Performance-related questions

8.1       What is the pull in range of the PTP loop and SyncE PLL?

8.2       Using the BMCA algorithm how long does it take to switch to a new master and what is the measurement criterion?

8.3       The cTE between my Master and Slave/Boundary Clock is very large - what could cause this?

8.4       How many slaves can this solution support and what are the dependent parameters?

8.5       What is DCO mode and how can it be exercised?

8.6       What OCXO vendor and part number do you recommend?

8.7       What type of reference oscillator should I use?

8.8       How can I estimate the power consumption of the Si5388/89?

9       SW-related questions

9.1       What operating system does the Si5388/89 solution run under?

9.2       What Linux kernel version does the SW use?

9.3       What modules does the SW in the Si5389 solution support?

9.4       What format is the SW delivered?

9.5       In the SW stack log (slabtimingptp2.log), what does “Average Clock Drift” value represent?

9.6       In the configuration file (e.g. slab_timing_ptp2_boundary_clock_G_8275_1_multicast.conf), what does “lock threshold” value represent?

9.7       After the kernel initializes, how can I check if I have all the HW IP blocks are present in my design?

9.8       When I try to bring up my Ethernet links via ifconfig I get a “segmentation fault” error – what could cause this?

9.9       When porting to Petalinux v2019.2, I’m not able to bring up the eth1, eth2 ports – what could the problem be?

10         FPGA-related questions

10.1     Can Silicon Labs provide source verilog files?

10.2     What Xilinx FPGA’s can Silicon Labs’ SW be ported to?

11         Ordering information questions

11.1     I can’t create an OPN for the Si5388/89 – why not?

The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.

Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.

Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.

*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.

Proper HCSL Termination Networks

Examples of Improper HCSL Termination Networks

In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.

An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.

It is okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled differential input format such as LVDS, LVPECL, or HCSL
• The clock is a DC coupled CMOS clock whose voltage levels are constrained to be within -1.0V and +3.8V.
• The clock is an AC coupled CMOS clock with a peak-to-peak swing <2.0V. Note that this peak-peak swing must take into account any overshoot or undershoot of the CMOS signal

It is not­ okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled CMOS clock with a peak-to-peak swing >2.0V. Note that this peak-to-peak swing must take into account any overshoot or undershoot of the CMOS signal.

Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.