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Si5388/89 IEEE 1588 FAQ's

RobertKaminsky | 10/286/2020 | 01:12 AM

1       Package Information. 4

1.1       Where can I get detailed material composition information on these devices?. 4

1.2       Is the part RoHS compliant?. 4

1.3       What is the Moisture Sensitivity Level (MSL) rating for the Si5388/89?. 4

1.4       What is the recommend profile for solder reflow process?. 4

2       PCB Design and Layout Guidance. 4

2.1       Where can I find the IBIS model for the Si5388/89?. 4

2.2       Do you have a list of recommended crystals?. 4

2.3       I don’t want to use a crystal with the Si5388/89. Can I use an XO or TCXO as the XA/XB reference instead? And if so, how do I interface an external oscillator to the device?. 4

3       ITU-T Standards-related questions. 4

3.1       What IEEE 1588 Profiles are included in the current solution. 4

3.2       Does this solution meet ITU G.8262 for SyncE and G.8262.1 for Enhanced SyncE?. 4

4       Evaluation system-related questions. 5

4.1       How do I get a complete evaluation system?. 5

4.2       What software is available for the evaluation system... 5

4.3       Why is a Xilinx FPGA evaluation board required?. 5

4.4       My Xilinx Carrier Card (ZCU102 or ZCU111) is not passing self-test – what could be wrong?. 5

5       System architecture-related questions. 5

5.1       What system architectures does this solution support?. 5

5.2       What clock configurations does the Si5388/89 solution support?. 5

6       Compliance-related questions. 5

6.1       Is a compliance report available?. 5

6.2       What type of reference clocks can you provide G.8273.2 compliance reports for?. 5

6.3       What class do you support for ITU-T G.8273.2 compliance?. 5

6.4       What ITU-T Recommendations do T-TSC (slave clocks) need to comply with?. 6

7       Device configuration-related questions. 6

7.1       What serial interfaces does the device support?. 6

7.2       Does the Si5388/89 support Zero-Delay Mode?. 6

7.3       Can the application FW and/or device configuration (i.e. Frequency Plan) be modified by the user independently and how is this done?. 6

7.4       Are there any restrictions on which DSPLL can be used for IEEE 1588 synchronization?. 6

7.5       Can I DCO a DSPLL that’s in Holdover/Free Run?. 6

7.6       The default frequency plan in the reference design feeds back an output from the SyncE PLL to source the PTP PLL – why is this done?. 6

7.7       My reference PLL is indicating that’s it’s not in lock. I’m providing a good XTAL and Reference clock – what could cause this? 6

7.8       Why can’t I see the Si5388/89 in the listing of Network Synchronizers in CBPro?. 7

7.9       I see that the Si5388/89 supports 1pps inputs – can I use this for an APTS application?. 8

7.10     What power sequencing is required?. 8

8       Performance-related questions. 9

8.1       What is the pull in range of the PTP loop and SyncE PLL?. 9

8.2       Using the BMCA algorithm how long does it take to switch to a new master and what is the measurement criterion?. 9

8.3       The cTE between my Master and Slave/Boundary Clock is very large - what could cause this?. 9

8.4       How many slaves can this solution support and what are the dependent parameters?. 10

8.5       What is DCO mode and how can it be exercised?. 10

8.6       What OCXO vendor and part number do you recommend?. 10

8.7       What type of reference oscillator should I use?. 10

8.8       How can I estimate the power consumption of the Si5388/89?. 10

8.9       Can I measure the junction temperature of the ‘88/’89?. 11

8.10     How can I measure the lock time for a 1pps input clock?. 11

8.11     Why does the time error increase when I add traffic to the link?. 11

8.12     My PTP engine is ‘sync’d’ but the Delay value is equal to ‘0’, what could cause this?. 12

9       SW-related questions. 12

9.1       What operating system does the Si5388/89 solution run under?. 12

9.2       What Linux kernel version does the SW use?. 12

9.3       What modules does the SW in the Si5389 solution support?. 12

9.4       What format is the SW delivered?. 12

9.5       In the SW stack log (slabtimingptp2.log), what does “Average Clock Drift” value represent?. 12

9.6       In the configuration file (e.g. slab_timing_ptp2_boundary_clock_G_8275_1_multicast.conf), what does “lock threshold” value represent?. 12

9.7       After the kernel initializes, how can I check if I have all the HW IP blocks are present in my design?. 12

9.8       When I try to bring up my Ethernet links via ifconfig I get a “segmentation fault” error – what could cause this?. 13

9.9       Do I need to provide an input to my SFP module for Port 1 in order to bring up the Ethernet links?. 13

9.10     When porting to Petalinux v2019.2, I’m not able to communicate with the Si5380 die – what could the problem be?. 13

9.11     What is the typical ‘time to synchronize’ after I start the stack and what could cause this to time to be excessive?. 13

9.12     When I probe the 1pps output from the FPGA (i.e. ToD output) it’s not 1Hz – what can cause this?. 13

9.13     What is “Holdover Interval”? Printed when requesting PTP time information ptp2config t i. 14

9.14     How can I dynamically change the clock class?. 14

10         FPGA-related questions. 14

10.1     Can Silicon Labs provide source verilog files?. 14

10.2     What Xilinx FPGA’s can Silicon Labs’ SW be ported to?. 14

11         Ordering information questions. 15
11.1        I can’t create an OPN for the Si5388/89 – why not? 15

Si5388-89-FAQ_Rev0.5.pdf