Si5351 has output channel up to 8 and each output has one Multisynth divider (MS). Please note MS0 to MS5 can support fractional and integer divider (from 8~900) while MS6 and MS7 only support integer divider (even integer divider from 6~254) (please refer to AN619 for detail information).
In addition to 8-channel version (20 QFN package), Si5351 also has 3-channel version (10MSOP package) and 4-channel version (16QFN package). The MS of 3-channel version is from MS0 to MS2 normally for CLK0 to CLK2. While please pay attention to mapping relationship between output and MS divider for 4-channel version. MS divider of CLK0/CLK1/CLK2 and CLK3 is MS1/MS2/MS5 and MS7. This leads to CLK3 min frequency can’t as low as 2.5KHz like CLK0/1/2. 18.75KHz is the min output frequency for CLK3 for 3-channel version.
The Low power LVPECL in Si5330x and Si5331x is pseudo-LVPECL which has different driver constructure with LVPECL and there is different termination for low power LVPECL. Please refer to below as DC coupling and AC coupling termination for low power LVPECL.
1. A input clock or crystal should be valid before you write a new configuration (register map) to the RAM of Si5338
2. Writing new values to the IC should follow read-modify-write process via write-allowed mask. Here is AN428 and source code about programming. https://www.silabs.com/documents/public/application-notes/AN428.pdf
If you’re not able to communicate to your module, neither over the serial interface nor over the network, possibly due to installing the wrong update file. It requires that you use the Commander program, that you can connect to the module’s serial port and that you have access to the module’s reset or can power cycle the device.
Please be noted that keep serial connection when you power cycle or reset the device. If your device/system are powered by USB that is also a serial port, you cannot plug out/plug in USB cable to power cycle the device. Because the serial connection will also be disconnected when you plug out/plug in USB cable. Please separate Serial port and power supply or use a reset signal for this case.
Timing Knowledge Base
Si5351 Multisynth divider mapping relationship and divider range
Si5351 has output channel up to 8 and each output has one Multisynth divider (MS). Please note MS0 to MS5 can support fractional and integer divider (from 8~900) while MS6 and MS7 only support integer divider (even integer divider from 6~254) (please refer to AN619 for detail information).
In addition to 8-channel version (20 QFN package), Si5351 also has 3-channel version (10MSOP package) and 4-channel version (16QFN package). The MS of 3-channel version is from MS0 to MS2 normally for CLK0 to CLK2. While please pay attention to mapping relationship between output and MS divider for 4-channel version. MS divider of CLK0/CLK1/CLK2 and CLK3 is MS1/MS2/MS5 and MS7. This leads to CLK3 min frequency can’t as low as 2.5KHz like CLK0/1/2. 18.75KHz is the min output frequency for CLK3 for 3-channel version.
Low power LVPECL termination for Si5330x and Si5331x buffer
The Low power LVPECL in Si5330x and Si5331x is pseudo-LVPECL which has different driver constructure with LVPECL and there is different termination for low power LVPECL. Please refer to below as DC coupling and AC coupling termination for low power LVPECL.
The termination of LVPECL please refer to https://www.silabs.com/community/timing/knowledge-base.entry.html/2019/01/17/lvpecl_output_driver-BkN2
Si5338 I2C Programming Tips
1. A input clock or crystal should be valid before you write a new configuration (register map) to the RAM of Si5338
2. Writing new values to the IC should follow read-modify-write process via write-allowed mask. Here is AN428 and source code about programming.
https://www.silabs.com/documents/public/application-notes/AN428.pdf
https://www.silabs.com/documents/public/software/AN428SW.zip
3. I2C timing:
Hold Time START Condition tHD:STA should bigger than 4us for standard mode and 0.6us for fast mode.
Data Hold Time tHD:DAT should bigger than 100ns for standard mode fast mode.
4. If you simulate I2C via FPGA, please configure SDA to inout. Set SDA as output when write data, and Set SDA as input when ACK send to FPGA.
A note for a brick M64/M68/M88 recovery
If you’re not able to communicate to your module, neither over the serial interface nor over the network, possibly due to installing the wrong update file. It requires that you use the Commander program, that you can connect to the module’s serial port and that you have access to the module’s reset or can power cycle the device.
Please be noted that keep serial connection when you power cycle or reset the device. If your device/system are powered by USB that is also a serial port, you cannot plug out/plug in USB cable to power cycle the device. Because the serial connection will also be disconnected when you plug out/plug in USB cable. Please separate Serial port and power supply or use a reset signal for this case.