This article is complementary of below application note for a crystal used as reference clock of Si534x/8x/9x that need a larger load capacitor. Customer can use below circuit for the design if XTAL is not equal 8pf.
Eg: if a XTAL request 12pf CL, then
C3 = 4 pf
With limitation of Keysight E5052B, it can't measure phase noise when the carrier frequency less than 250MHz.
If one application need to see the phase noise at 100MHz while the carrier frequency is less than 250MHz, then they may need below two methods:
1. Test the frequency directly, and simply use the phase noise number at 40MHz or 20MHz, usually the far end to 100MHz phase noise trace is the extensions.
2. Double or quadruple the carrier frequency to make sure the carrier frequency larger than 250MHz and now you can the span of E5052B to 100MHz, and then plus 6 and 12 to get the actual carrier frequency phase noise. (Note: phase noise decreased by 6db every twice, it comes from a simplified function 20lg(f2/f1) ).
There is some tables to show the I2C data protocol in datasheet. Here is some figures to illustrate the protocol clearly.
1. Block Read
2. Block Write
3. Byte Read
Please be noted that Si53152/4/6/9 all need a valid input clock in order for the I2C interface to work.
CBPro implements the DCO function on a Si5395/94/92/45/44/42 by changing the numerator (Nx_NUM) as this gives a higher resolution than changing the N divider denominator (Nx_DEN). However the DCO function can be implemented by changing the Nx_DEN value and this KB article describes how to do this. Note that when changing the Nx_DEN value instead of the Nx_NUM value the minimum step size will increase by approximately the Nx divider value. This is because the Nx_NUM register is 44 bits and the Nx_DEN register is 32 bits. Changing the Nx_NUM term causes an extremely small non-linearity, which will not be a problem except for very rare applications. Changing the Nx_DEN term does not cause any non-linearity.
The DCO function of Si5395/94/92/45/44/42 devices is implemented by changing the Nx_DEN value in one of two ways:
Here is the procedure to implement a DCO function by changing the Nx_DEN term:
More information about DCO applications for Si5395/94/92/45/44/42 can be found at:
The Si5395/94/92/91/45/44/42/41 parts have a maximum output frequency of 1028 MHz. However, there are a few gaps below 1028 MHz which are not valid output frequencies. Why is this the case?
The output clock frequency is equal to the VCO frequency divided down by an output divider. Below 720 MHz, the output divider is able to operate in either fractional or integer mode. Therefore, any output frequency below 720 MHz can be synthesized. Above 720MHz, however, the output divider must be equal to an even integer value, with an exception made for the odd value of Fvco/Fout = 15. The dual constraints of an even integer divide ratio and a limited VCO tuning range lead to a couple of small gaps in the allowed output frequencies. More specifically, the frequencies from 720 MHz --> 733.334 MHz and 800 MHz --> 825 MHz are not valid output frequencies. The figure below shows a conceptual diagram of the valid and non-valid output frequency ranges. The blue areas show the valid output frequency ranges, and the red areas show the non-valid output frequency ranges.
The above definition of the valid and non-valid output frequency ranges holds true only if one unique frequency from the upper frequency range (720 MHz --> 1028 MHz) exists in the frequency plan. This is because selecting an output frequency from the 720 MHz --> 1028 MHz range fixes the VCO frequency. Therefore, selecting two or more unique output frequencies (noting that they both require integer dividers) from the upper range may present competing requirements for the VCO frequency and hence result in a non-synthesizable frequency plan.
A few examples of valid and non-valid frequency plans are listed below:
People sometimes mix the definitions of Time Interval Error (TIE) jitter and period jitter and easily make a common mistake of calculating TIE jitter but with period jitter formula for a spread spectrum clock (SSC). Let's denote the clock frequency as F, the down spread linear modulation as d, the modulation rate as fm, and then the increase of peak to peak value of period jitter due to spread spectrum is given by:
PJpp = d/((1-d)F);
the increase of peak to peak value of TIE jitter due to spread spectrum is given by:
TIEJpp = d/(8fm).
Take a PCIe SSC as an example: F = 100MHz, d = 0.5% (down spread), fm = 30KHz - 33KHz. It gives a PJpp of 0.05 ns and a TIEJpp of 18.9ns - 20.8ns.
Regarding DDR design, there are some clock such as 33.333333...MHz, 133.333333...MHz and 166.666666...MHz etc. Generally 33.333333MHz, 133.333333MHz and 1666.666666MHz are used to approximate value. This method will introduce more spurs and less accuracy.
Silicon Labs Multisynth technology can support 100MHz/3, 400MHz/3 and 500M/3 configuration to get exact clock with 0ppm. This configuration can reduce spurs as well.
The recommended termination is shown below.
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedance and drive strengths. A series source termination resistor (Rs) is recommended close to the output to match the selected output impedance to the trace impedance (Rs = Trace Impedance – Zs). For example, the driver impedance Zs is configured to 38 Ohm, and the trace impedance is 50 Ohm. So the Rs is 12 Ohm.
1. If you change output impedance, please change Rs accordingly.
2. Use of the complementary CMOS for one pair OUTx/OUTxb is recommended to help balance the output current surges during transitions. It will reduce the crosstalk noise for adjacent channel.
3. Generally, the lowest impedance for a given supply voltage is preferable, since it will give the fastest edge rates. The faster edge rate means more crosstalk noise to adjacent channel. If the jitter performance of adjacent channel is high priority, the higher impedance should be selected to reduce the noise.
These transients can be removed by the following process
1. Set OUT_PDN_ALL = 1 (0x0145 = 1) before any registers of the new plan are written
2. Just before the post amble is written (after all the other writes), set OUT_PDN_ALL = 0 (0x0145 = 0)