Si5351 has output channel up to 8 and each output has one Multisynth divider (MS). Please note MS0 to MS5 can support fractional and integer divider (from 8~900) while MS6 and MS7 only support integer divider (even integer divider from 6~254) (please refer to AN619 for detail information).

In addition to 8-channel version (20 QFN package), Si5351 also has 3-channel version (10MSOP package) and 4-channel version (16QFN package). The MS of 3-channel version is from MS0 to MS2 normally for CLK0 to CLK2. While please pay attention to mapping relationship between output and MS divider for 4-channel version. MS divider of CLK0/CLK1/CLK2 and CLK3 is MS1/MS2/MS5 and MS7. This leads to CLK3 min frequency can’t as low as 2.5KHz like CLK0/1/2. 18.75KHz is the min output frequency for CLK3 for 3-channel version.

The Low power LVPECL in Si5330x and Si5331x is pseudo-LVPECL which has different driver constructure with LVPECL and there is different termination for low power LVPECL. Please refer to below as DC coupling and AC coupling termination for low power LVPECL.

The termination of LVPECL please refer to https://www.silabs.com/community/timing/knowledge-base.entry.html/2019/01/17/lvpecl_output_driver-BkN2

1. A input clock or crystal should be valid before you write a new configuration (register map) to the RAM of Si5338
2. Writing new values to the IC should follow read-modify-write process via write-allowed mask. Here is AN428 and source code about programming.
https://www.silabs.com/documents/public/application-notes/AN428.pdf

https://www.silabs.com/documents/public/software/AN428SW.zip

3. I2C timing: 

Hold Time START Condition tHD:STA should bigger than 4us for standard mode and 0.6us for fast mode.

Data Hold Time tHD:DAT should bigger than 100ns for standard mode fast mode.

4. If you simulate I2C via FPGA,  please configure SDA to inout. Set SDA as output when write data, and Set SDA as input when ACK send to FPGA.

If you’re not able to communicate to your module, neither over the serial interface nor over the network, possibly due to installing the wrong update file. It requires that you use the Commander program, that you can connect to the module’s serial port and that you have access to the module’s reset or can power cycle the device. 

Please be noted that keep serial connection when you power cycle or reset the device. If your device/system are powered by USB that is also a serial port, you cannot plug out/plug in USB cable to power cycle the device. Because the serial connection will also be disconnected when you plug out/plug in USB cable. Please separate Serial port and power supply or use a reset signal for this case. 

1       Package Information. 4

1.1       Where can I get detailed material composition information on these devices?. 4

1.2       Is the part RoHS compliant?. 4

1.3       What is the Moisture Sensitivity Level (MSL) rating for the Si5388/89?. 4

1.4       What is the recommend profile for solder reflow process?. 4

2       PCB Design and Layout Guidance. 4

2.1       Where can I find the IBIS model for the Si5388/89?. 4

2.2       Do you have a list of recommended crystals?. 4

2.3       I don’t want to use a crystal with the Si5388/89.  Can I use an XO or TCXO as the XA/XB reference instead?  And if so, how do I interface an external oscillator to the device?. 4

3       ITU-T Standards-related questions. 4

3.1       What IEEE 1588 Profiles are included in the current solution. 4

3.2       Does this solution meet ITU G.8262 for SyncE and G.8262.1 for Enhanced SyncE?. 4

4       Evaluation system-related questions. 5

4.1       How do I get a complete evaluation system?. 5

4.2       What software is available for the evaluation system... 5

4.3       Why is a Xilinx FPGA evaluation board required?. 5

4.4       My Xilinx Carrier Card (ZCU102 or ZCU111) is not passing self-test – what could be wrong?. 5

5       System architecture-related questions. 5

5.1       What system architectures does this solution support?. 5

5.2       What clock configurations does the Si5388/89 solution support?. 5

6       Compliance-related questions. 5

6.1       Is a compliance report available?. 5

6.2       What type of reference clocks can you provide G.8273.2 compliance reports for?. 5

6.3       What class do you support for ITU-T G.8273.2 compliance?. 5

6.4       What ITU-T Recommendations do T-TSC (slave clocks) need to comply with?. 6

7       Device configuration-related questions. 6

7.1       What serial interfaces does the device support?. 6

7.2       Does the Si5388/89 support Zero-Delay Mode?. 6

7.3       Can the application FW and/or device configuration (i.e. Frequency Plan) be modified by the user independently and how is this done?. 6

7.4       Are there any restrictions on which DSPLL can be used for IEEE 1588 synchronization?. 6

7.5       Can I DCO a DSPLL that’s in Holdover/Free Run?. 6

7.6       The default frequency plan in the reference design feeds back an output from the SyncE PLL to source the PTP PLL – why is this done?. 6

7.7       My reference PLL is indicating that’s it’s not in lock.  I’m providing a good XTAL and Reference clock – what could cause this?  6

7.8       Why can’t I see the Si5388/89 in the listing of Network Synchronizers in CBPro?. 7

7.9       I see that the Si5388/89 supports 1pps inputs – can I use this for an APTS application?. 8

7.10     What power sequencing is required?. 8

8       Performance-related questions. 9

8.1       What is the pull in range of the PTP loop and SyncE PLL?. 9

8.2       Using the BMCA algorithm how long does it take to switch to a new master and what is the measurement criterion?. 9

8.3       The cTE between my Master and Slave/Boundary Clock is very large - what could cause this?. 9

8.4       How many slaves can this solution support and what are the dependent parameters?. 10

8.5       What is DCO mode and how can it be exercised?. 10

8.6       What OCXO vendor and part number do you recommend?. 10

8.7       What type of reference oscillator should I use?. 10

8.8       How can I estimate the power consumption of the Si5388/89?. 10

8.9       Can I measure the junction temperature of the ‘88/’89?. 11

8.10     How can I measure the lock time for a 1pps input clock?. 11

8.11     Why does the time error increase when I add traffic to the link?. 11

8.12     My PTP engine is ‘sync’d’ but the Delay value is equal to ‘0’, what could cause this?. 12

9       SW-related questions. 12

9.1       What operating system does the Si5388/89 solution run under?. 12

9.2       What Linux kernel version does the SW use?. 12

9.3       What modules does the SW in the Si5389 solution support?. 12

9.4       What format is the SW delivered?. 12

9.5       In the SW stack log (slabtimingptp2.log), what does “Average Clock Drift” value represent?. 12

9.6       In the configuration file (e.g. slab_timing_ptp2_boundary_clock_G_8275_1_multicast.conf), what does “lock threshold” value represent?. 12

9.7       After the kernel initializes, how can I check if I have all the HW IP blocks are present in my design?. 12

9.8       When I try to bring up my Ethernet links via ifconfig I get a “segmentation fault” error – what could cause this?. 13

9.9       Do I need to provide an input to my SFP module for Port 1 in order to bring up the Ethernet links?. 13

9.10     When porting to Petalinux v2019.2, I’m not able to communicate with the Si5380 die – what could the problem be?. 13

9.11     What is the typical ‘time to synchronize’ after I start the stack and what could cause this to time to be excessive?. 13

9.12     When I probe the 1pps output from the FPGA (i.e. ToD output) it’s not 1Hz – what can cause this?. 13

9.13     What is “Holdover Interval”?  Printed when requesting PTP time information ptp2config t i. 14

9.14     How can I dynamically change the clock class?. 14

10         FPGA-related questions. 14

10.1     Can Silicon Labs provide source verilog files?. 14

10.2     What Xilinx FPGA’s can Silicon Labs’ SW be ported to?. 14

11         Ordering information questions. 15

Since power supply limitation, sometimes we need convert CMOS signal level to meet receiver requirement. Such as 3.3V to 2.5V, 1.8V to 1.2V

Please refer to below interfacing from AN408 for this conversion.

This resistor attenuator network should consider device source impedance Rs (usually this information can be found in datasheet). The R1 and R2 calculation should consider below two items:

1. R2 parallel with R1+ Rs to get 50 ohms resistor for impedance matching.

2. R2 /(R1+Rs) equal to ratio of receiver swing/ source swing

Attachment is one excel tool to calculate R1 and R2 according to source/receiver level and source impedance

In the Si5395-91 & Si5345-40 devices, DCO mode is intended to be used within the range of +/-350ppm. It is possible to use DCO mode beyond this range, but it is important to be aware of the following caveats:

• DCO mode works according to the following equation

where Fvco is the VCO frequency, NDEN is the N-divider denominator, NNUM is the N-divider numerator, NNUM,DELTA is the value which the numerator is being incremented/decremented by per step, X is the net amount of steps applied, and R is the integer R-divider value. If DCO mode is operated within a narrow frequency range, Fout has an approximately linear relation to X. However, as the frequency range increases, Fout becomes increasingly nonlinear with respect to X. Consequently, the actual frequency step size will be significantly different from the desired step size as the N-divider is continually incremented/decremented.

• ClockBuilder Pro optimizes the value of the N-divider to avoid noisy values of N within the +/-350ppm range when DCO mode is enabled. Beyond the +/-350ppm range, the N-divider may land on noisy values of N, thus degrading the noise performance of the device.

The following are the recommended solutions to address the above issues:

• DCO mode may be configured to increment/decrement the NDEN instead of NNUM. This results in a perfectly 1st order polynomial relation between Fout and X. However, NDEN has less resolution than NNUM, so the minimum resolution of DCO mode will be higher in this case. Although incrementing NDEN results in a perfectly linear step, it does not solve the noise issues related to using DCO mode over a large frequency range. Please contact Silicon Labs customer support to implement this solution.
• Using Frequency-on-the-Fly (FOTF) not only results in perfectly linear steps, but also optimizes the frequency plan to avoid noisy N-divider values across the entire range of desired frequencies. For example, if the desired output is 50MHz to 100MHz in 1MHz steps, Frequency-on-the-Fly will give far superior noise performance to DCO mode and give perfectly linear steps.

For more details on DCO mode and FOTF, please refer to the following application notes:

• DCO Mode with Si5395/94/92/45/44/42: https://www.silabs.com/documents/public/application-notes/an858-dco-applications-jitter-attenuators.pdf
• DCO Mode with Si5391/41/40: https://www.silabs.com/documents/public/application-notes/AN959.pdf
• Frequency-on-the-Fly: https://www.silabs.com/documents/public/application-notes/an1178-frequency-otf-jitter-atten-clock-gen.pdf

The Si534x/7x/8x/9x clock generators and jitter attenuators can generate clocks compatible with HCSL receivers. However, the designer must be careful not to use conventional HCSL termination networks but rather follow the recommended HCSL termination in the reference manual.

Conventional HCSL relies on steering a 15mA current across two 50 ohm resistors to ground, which generates the high and low levels of roughly 750mV and 0mV respectively. In contrast, the Si534x/7x/8x/9x driver generates the proper HCSL voltage swing on the driver side and then AC couples that signal to a 50 ohm (Thevenin) resistor divider network to set the proper HCSL common-mode level of about 0.375V at the receiver side.

Figure 1 shows proper HCSL termination for Si534x/7x/8x/9x devices, copied from the reference manual. Figures 2-4 show examples of commonly used HCSL termination networks which should not be used for Si53x4/x7/x8/9x devices.

*Please note that other product families in the Silabs timing portfolio may have different methods of terminating HCSL clocks, and the documentation will provide the proper termination network.

Proper HCSL Termination Networks

Examples of Improper HCSL Termination Networks

In this article, an input is considered unused when that input is declared as “Unused (Powered-down)” in ClockBuilder Pro.

An active clock signal on an unused input must not violate the maximum and minimum voltage level at the input pins, which are +3.8V and -1.0V respectively. Permanent device damage may occur if the absolute maximum ratings are exceeded. If the unused input is AC coupled, then input pin will be biased at 0V. Therefore, the maximum peak-to-peak swing of the AC coupled input must not be greater than 2Vpp [0V – 2Vpp/2 = -1V] so that the signal does not fall below -1.0V. See below figure for example scenarios.

It is okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled differential input format such as LVDS, LVPECL, or HCSL
• The clock is a DC coupled CMOS clock whose voltage levels are constrained to be within -1.0V and +3.8V.
• The clock is an AC coupled CMOS clock with a peak-to-peak swing <2.0V. Note that this peak-peak swing must take into account any overshoot or undershoot of the CMOS signal

It is not­ okay to provide an active clock signal to an unused input if:

• The clock is an AC coupled CMOS clock with a peak-to-peak swing >2.0V. Note that this peak-to-peak swing must take into account any overshoot or undershoot of the CMOS signal.

Whether an input is unused or enabled, the absolute maximum/minimum ratings cannot be violated. The designer must take into account any overshoot/undershoot in the signal, any temperature related effects that could cause increased overshoot/undershoot, or any uncertainty in the signal amplitude. It is always advised to leave some margin to minimize potential risks.

A HCSL clock can be applied at IN2, IN1, or IN0 of Si5341. Regarding to the termination, just use an AC blocking cap in series with each input. This is present a high impedance to the PCB trace and should be what the customer needs since they have source side impedance matching. You can remove the 100 Ohm resistor between IN+ and IN- if the source is terminated properly.

Or you can put the 100 Ohm resistor on the other side of the AC coupling caps but keep the 100 Ohm resistor within 5 mm of the input pins.