This KBA article describes on how to connect your custom made board based on BGM/EFR32 device to Simplicity Studio via JTAG or SWD interface.
To start you need to connect your device via the WSTK using the simplicity debug connector. To accomplish this you can check our application note AN958: Debugging and Programming Interfaces for Custom Designs. This note, together with the data-sheet of your device, will help you correctly connect the device to be debugged/Flashed using the WSTK and the Simplicity Studio.
After your device is correctly connected, you will need to follow the following steps:
Inside the Simplicity Studio environment, go to the simplicity commander
Then choose the J-Link device (WSTK) click connect to Adapter, afterwards change debug interface to JTAG/SWD and press connect to Target(without changing the device, it will change by itself).
It should connect and show the information of the device.
Now copy the device name that appeared (EFR32XGX), close the simplicity commander and go to your device configuration by right clicking on J-Link Silicon labs in the debug adapters tab, in the Launcher view of Simplicity Studio. Paste the device name in the target part and replace the one that you previously had. Choose JTAG as target interface.
Afterwards, go into the Adapter Configuration tab and in the Debug Mode drop-down menu choose OUT. Finish by clicking OK.
Now you should be able to flash to the device using the Simplicity Studio and debug your device.
Note: if you are using a BGM device you may get a warning "The part is different from the desired part but in the same part family. Select it with care at your own risk." Just ignore these warnings, if you choose remember my decision it will not show these warnings again.
This KBA describes how to debug your board and project in case you are experiencing "the device is not responding" issue when connecting the BGTool to your NCP target device.
The "not responding" error is received when BGTool is not able to communicate with the module using BGAPI messages over the UART interface. Normally when you click "connect" on BGTool: BGTool will try to read the BT device address of the target device. if there's no response, then you get the "not responding" popup.
The issue might be caused by:
The easiest method to be used in radio boards: flash a pre-built NCP-empty demo to the board. Since the demos are already tested and come with all the required configurations to be used as it is.
If you are using a custom board please Verify that the UART settings in your firmware align correctly with your custom board. In case you are not using the VCOM, make sure it is disabled in the hal-config.h file. If possible check with a logic analyzer or probe that the UART lines are correctly connected in your custom board.
Verify that the configuration of your device matches the one you are using in the BGTool, by default the BGTool uses a 115200 baud rate and no flow control.
You can check the device VCOM settings using the console in Studio, following this article KBA_BT_1208: Using virtual COM port (VCOM)
The default settings are: baud rate 115200, flow control = "auto".
If you radio board is unresponsive might be caused by a lack of bootloader. Please add the gecko bootloader to your device and project. Follow this article: KBA_BT_0603: Adding Gecko Bootloader to Bluetooth projects
It might also happen that BGTool simply gets out of sync (e.g. due to UART buffer overflow), and it cannot find the beginning of the BGAPI packets. There is no special character at the beginning of the packets, so it cannot resynchronize. In this case resetting the device and BGTool may help.
Sometimes just resetting the device is not enough, so unplugging and replugging the USB cable and power cycling your device is recommended.
xGM based SiP packages are custom designed packages which are unique in design and offers great performance with the smallest PCB area. As the package design is not standard, special attention needs to be given during assembly as the processes involved are similar to that of QFN packages, but there are some subtle changes that the designer and contract manufacturer needs to follow.
Solder – shorts/voids/cold joints, part damage due to MSL violation, solder bridge, copper corrosion are some of the general assembly issues that exist due to the improper assembly processes.
This KBA will help to identify steps involved in designing an application with xGM based SiP along with some guidance that will help the user while assembling these custom designed parts in their application. Please note that some of the design and assembly guidelines are in general terms and can also be applied to other parts with standard packages.
[PHASE I] Designing:
Printed Circuit Board:
All our reference radio boards are built on ENIG (Electroless Nickel/Immersion Gold) type PCB. For a 4-layer board, the recommended distance between Top - Inner layer 1 and Inner Layer 2 – Bottom layer of the board should be close to 300 µm.
Changing any of the PCB parameters will change its effect on RF performance. For e.g., If the distance between the two layers is changed then the PCB parasitic will change which in return changes the impedance for the RF path.
PCB footprint / PCB Land Pattern Vs Package Dimensions:
Many users get confused between the term PCB footprint and Package Dimension. Package dimension is the dimension between various X, Y coordinates of the part such as spacing between two pads, size of pads, the distance between the top most and bottom most pad on one side of the chip, etc. Whereas the PCB land pattern shows the recommended pad dimension that should be used in the layout of the PCB, it also shows the recommended keep-out area dimensions for the antenna loop. The package will be soldered to the PCB land pattern available on the PCB during the assembly process.
It is always recommended to refer the latest datasheet for the updated recommended land pattern in your design. Failure to use the correct land pattern can result in assembly issues.
Solder mask is a material that is used to coat the board to do the following:
The openings in the solder mask layer allow the solder to be applied, whereas the remaining area is exposed to the solder resist ink which does not allow the solder paste to get applied. Usually, the size of the opening in the solder mask layer is bigger than the size of the pads of the part being used. The solder mask layer becomes very important during the assembly of the SiP because, the solder mask between the leads acts as a dam, keeping the solder from bridging across pads.
If the size of the opening is too much larger than the pad, then the larger area is exposed to the environment and the distance between two pads covered by the solder mask will be very small. This can cause the forming of solder bridges and thereby shorting two pins. Similarly, if the size of the opening is smaller than the pad, then there will be very little area left for the paste mask to allow solder paste to be applied on the pad leading to assembly issues.
The size of the opening also depends upon the tolerance of the instrument used by the PCB fabrication house. The fabrication house having a higher tolerance will result in significant offsets of the openings in these layers with respect to the pads. If the openings are not large enough in the solder mask, a portion of the mask may cover the pads. The fabrication house having a tighter tolerance on the placement of the solder mask openings and so same size openings as pad dimensions are possible but may depend on the capability and offerings of the specific PCB fabrication house.
Hence some initial trial runs might be required to determine the correct size of the openings in the solder mask layer.
Paste mask layer represents the solder paste stencil that is used in SMD PCB layouts. Openings in the paste mask layer will determine where the tin paste will be coated on the SMD pads. This coated tin paste allows the part to get attached to the paste that was applied on the PCB. Usually, the openings in the paste mask layer are of the same size or smaller size than the pads of the part. The size of the opening and thickness of the stencil will determine the amount of solder paste that will be applied. Too much or too little of solder, both are undesired and can create issues while doing the assembly.
In the above figure, the solder mask opening will expose the copper pad or trace to the environment, whereas the area covered by the solder mask will be prevented from getting oxidized and corroded. As the paste mask opening is smaller than the pad dimension, solder paste will be applied only to the area represented in the dark blue color of the pad.
Please note that the dimensions for solder mask and paste mask given in the datasheet are as per the recommendation of our contract manufacturer that works best with their manufacturing equipment and technology and can be used as a starting point for custom designs. In any case, the user should work with their contract manufacturer and make necessary changes in the dimensions of these layers as per their machines and equipment.
Filled and Plated Vias:
Any vias that are on pads should be filled and plated. Plated vias ensures and maintains a solid connection and provides better conductibility.
If the vias are not filled, then during assembly the solder paste will seep into the via hole and will leave minimum solder at the pad and thus the pad may not be soldered to the PCB. This may make the surface uneven and thus the SiP might not get soldered properly.
If you decide not to use filled and plated vias, then make sure that you do not place the vias at the Antenna or GND pad and instead you should place it near these pads to avoid any possible assembly issues.
Solder Paste Type:
Once the SiP has been soldered, the pads of the SiP are not exposed to the user, which makes it difficult to clean the residuals of the solder paste or impossible to clean 100% residual under the SiP. To avoid or minimize the cleaning efforts after assembly, datasheet recommends a no clean, type -3 solder paste. A no-clean solder paste ensures that the residual of solder paste from the assembly reflow does not corrode the copper pad/trace thus, the residual can be left as it is without the need of cleaning it.
If there are any changes in the solder paste type, the user must make sure the 'no clean' specification is maintained. Solder paste types that are not specified as no-clean are assumed to contain solder flux which is corrosive and for which will need to be completely removed from the assembly. The cost and difficulty involved with removing 100% of the residual material from the SiP assembly make using these types of solder paste neither practical nor economic.
[PHASE II] Assembly:
Every individual part has its own soldering recommendation; hence it is recommended to follow the information given in the respective datasheets. All of our SiP modules are compatible with JEDEC standard and thus every contract manufacturer should strictly follow JEDEC/IPC J-STD-020, IPC-SM-782, and IPC 7351 guidelines.
Stencil Thickness (Refer to Contract Manufacturer):
The thickness of stencil affects the amount of the paste applied on the PCB. Silicon Labs recommends stencil thickness as 4mils. However, Stencil thickness can change as per the contract manufacturer's process and equipment. Thus, the dimension of the paste mask and solder mask layers should be tried and adjusted based on the result. It is expected for many custom designs, the correct dimension can only be found out after running a few trials on the assembly line.
Moisture Sensitivity Level (MSL) rating:
Verifying moisture sensitivity level rating is very important before assembling the parts because, once the parts have been exposed to moisture for more than the rated time, the parts become susceptible to moisture which develops inside the package. If moisture gets developed inside the SiP, during assembly the moisture molecules will expand quickly into steam which will displace the internal structure and composition of the SiP, thereby destroying the electrical integrity of the parts by forming solder shorts/ solder opens and making the part nonfunctional. Hence, in such cases, the baking procedure mentioned in the JEDEC standard should be strictly followed before assembling the parts.
Most of the Silicon Labs modules are qualified for MSL-3 rating, this information can be verified at the ordering label of the received package. Every package has a bag of desiccant and a moisture sensitive strip in it. This moisture sensitive strip can be used to verify the MSL-3 rating validity.
Temperature Profile (refer JEDEC standard):
The temperature profile of the part is a very important parameter that must be taken into consideration while assembling the parts. Temperature profiles provide information such as variations in temperature and different amounts of time the part should be held at different temperatures. The profile information makes sure that the temperature is enough to wet the pads, melt the solder and form a perfect solder joint between the device and PCB. The temperature for all of the parts on the PCB has to be considered for the temperature profile, hence the contract manufacturer will have to decide a common ground for the temperature based on their experience with the particular revision of custom PCB.
Failure to reach the optimum temperature for an improper amount of time can cause assembly problems. If the temperature is too low, then there can be cold solder joints between pads of IC and PCB. Similarly, If the temperature is too high, then the part can get damaged.
All of the Silicon Labs modules are compatible with JEDEC standard. It is highly recommended to follow JEDEC/IPC J-STD-020, IPC-SM-782, and IPC 7351 guidelines to avoid any assembly issues.
No. of allowable reflow:
Sometimes a PCB must be reflowed multiple times based on the nature of the design and components used or limitations of the assembly line. During a single reflow cycle, every component is exposed to and stressed with high temperature. Exposing parts to high temperature for multiple times can damage the parts. It is always recommended to avoid more than two reflow cycles of the parts.
X-Ray to verify connections:
It is always recommended to start a small number of prototype boards and prove out the assembly process using datasheet recommendations as a starting point. X-Rays of prototype boards have proven to be very useful in determining the quality of solder and connections between the pads and PCB. This can be done under a high-quality X-ray machine that can show if there are any solder blobs, excess of solder, solder voids or solder shorts. If there are any changes required, then various board iterations should be carried out. Once the quality of the assembly is verified, then large quantity production can be started.
Whether you are just getting started with Bluetooth Mesh or you are a more advanced user you have come to the right place.
This article aggregates training content which has been created by Silicon Labs, as well as material from the Bluetooth SIG itself to learn more about Bluetooth Mesh.
The content is organized in a logical sequence which assumes no previous knowledge of Bluetooth Mesh. You can get started with some of the material that introduces the basic Bluetooth Mesh concepts and walk your away to more advanced topics such as LPN/Friend and using the Network Analyzer to capture Bluetooth Mesh traffic.
This comprehensive technology overview explains some of the key concepts and terminology, system architecture, and security mechanisms, as well as the unique message publication and delivery technique behind Bluetooth mesh networking.
This Silicon Labs White paper gives a more in depth overview which complements the information presented in the SIG’s Bluetooth Mesh Networking Introduction above.
This paper provides a guided tour of Bluetooth mesh models.
This document provides step-by-step instructions to demonstrate a basic Bluetooth mesh network using the standard sample apps from the Bluetooth Mesh SDK and our mobile application.
In this document we discuss the basics of Bluetooth mesh required to understand the example and walk through key aspects of the application source code.
In this slide deck we go deeper into the code walkthrough with line by line explanation of the functionality for both the light and switch sample apps in the Bluetooth Mesh SDK.
Introduction of LPN and Friend node concepts by the Bluetooth SIG.
In depth explanation of how LPN and Friend nodes work with practical examples and Energy Profiler traces.
This is a 2-part article about Bluetooth Mesh provisioning covering all they key concepts.
This training deck shows how to user Silicon Labs Network Analyzer to capture, decode and analyze Bluetooth Mesh traffic data
This user guide explains how to use the Bluetooth SDK’s Node Configurator.
This application note goes through a series of network performance tests for Bluetooth Mesh.
This application note walks through the mobile ADK solution for Android and iOS with usage instructions and walkthrough of several APIs.
In addition to these you can browse through some of the Bluetooth Mesh KBAs listed in the Bluetooth Knowledge Article List section .