xGM based SiP packages are custom designed packages which are unique in design and offers great performance with the smallest PCB area. As the package design is not standard, special attention needs to be given during assembly as the processes involved are similar to that of QFN packages, but there are some subtle changes that the designer and contract manufacturer needs to follow.
Solder – shorts/voids/cold joints, part damage due to MSL violation, solder bridge, copper corrosion are some of the general assembly issues that exist due to the improper assembly processes.
This KBA will help to identify steps involved in designing an application with xGM based SiP along with some guidance that will help the user while assembling these custom designed parts in their application. Please note that some of the design and assembly guidelines are in general terms and can also be applied to other parts with standard packages.
[PHASE I] Designing:
Printed Circuit Board:
All our reference radio boards are built on ENIG (Electroless Nickel/Immersion Gold) type PCB. For a 4-layer board, the recommended distance between Top - Inner layer 1 and Inner Layer 2 – Bottom layer of the board should be close to 300 µm.
Changing any of the PCB parameters will change its effect on RF performance. For e.g., If the distance between the two layers is changed then the PCB parasitic will change which in return changes the impedance for the RF path.
PCB footprint / PCB Land Pattern Vs Package Dimensions:
Many users get confused between the term PCB footprint and Package Dimension. Package dimension is the dimension between various X, Y coordinates of the part such as spacing between two pads, size of pads, the distance between the top most and bottom most pad on one side of the chip, etc. Whereas the PCB land pattern shows the recommended pad dimension that should be used in the layout of the PCB, it also shows the recommended keep-out area dimensions for the antenna loop. The package will be soldered to the PCB land pattern available on the PCB during the assembly process.
It is always recommended to refer the latest datasheet for the updated recommended land pattern in your design. Failure to use the correct land pattern can result in assembly issues.
Solder mask is a material that is used to coat the board to do the following:
The openings in the solder mask layer allow the solder to be applied, whereas the remaining area is exposed to the solder resist ink which does not allow the solder paste to get applied. Usually, the size of the opening in the solder mask layer is bigger than the size of the pads of the part being used. The solder mask layer becomes very important during the assembly of the SiP because, the solder mask between the leads acts as a dam, keeping the solder from bridging across pads.
If the size of the opening is too much larger than the pad, then the larger area is exposed to the environment and the distance between two pads covered by the solder mask will be very small. This can cause the forming of solder bridges and thereby shorting two pins. Similarly, if the size of the opening is smaller than the pad, then there will be very little area left for the paste mask to allow solder paste to be applied on the pad leading to assembly issues.
The size of the opening also depends upon the tolerance of the instrument used by the PCB fabrication house. The fabrication house having a higher tolerance will result in significant offsets of the openings in these layers with respect to the pads. If the openings are not large enough in the solder mask, a portion of the mask may cover the pads. The fabrication house having a tighter tolerance on the placement of the solder mask openings and so same size openings as pad dimensions are possible but may depend on the capability and offerings of the specific PCB fabrication house.
Hence some initial trial runs might be required to determine the correct size of the openings in the solder mask layer.
Paste mask layer represents the solder paste stencil that is used in SMD PCB layouts. Openings in the paste mask layer will determine where the tin paste will be coated on the SMD pads. This coated tin paste allows the part to get attached to the paste that was applied on the PCB. Usually, the openings in the paste mask layer are of the same size or smaller size than the pads of the part. The size of the opening and thickness of the stencil will determine the amount of solder paste that will be applied. Too much or too little of solder, both are undesired and can create issues while doing the assembly.
In the above figure, the solder mask opening will expose the copper pad or trace to the environment, whereas the area covered by the solder mask will be prevented from getting oxidized and corroded. As the paste mask opening is smaller than the pad dimension, solder paste will be applied only to the area represented in the dark blue color of the pad.
Please note that the dimensions for solder mask and paste mask given in the datasheet are as per the recommendation of our contract manufacturer that works best with their manufacturing equipment and technology and can be used as a starting point for custom designs. In any case, the user should work with their contract manufacturer and make necessary changes in the dimensions of these layers as per their machines and equipment.
Filled and Plated Vias:
Any vias that are on pads should be filled and plated. Plated vias ensures and maintains a solid connection and provides better conductibility.
If the vias are not filled, then during assembly the solder paste will seep into the via hole and will leave minimum solder at the pad and thus the pad may not be soldered to the PCB. This may make the surface uneven and thus the SiP might not get soldered properly.
If you decide not to use filled and plated vias, then make sure that you do not place the vias at the Antenna or GND pad and instead you should place it near these pads to avoid any possible assembly issues.
Solder Paste Type:
Once the SiP has been soldered, the pads of the SiP are not exposed to the user, which makes it difficult to clean the residuals of the solder paste or impossible to clean 100% residual under the SiP. To avoid or minimize the cleaning efforts after assembly, datasheet recommends a no clean, type -3 solder paste. A no-clean solder paste ensures that the residual of solder paste from the assembly reflow does not corrode the copper pad/trace thus, the residual can be left as it is without the need of cleaning it.
If there are any changes in the solder paste type, the user must make sure the 'no clean' specification is maintained. Solder paste types that are not specified as no-clean are assumed to contain solder flux which is corrosive and for which will need to be completely removed from the assembly. The cost and difficulty involved with removing 100% of the residual material from the SiP assembly make using these types of solder paste neither practical nor economic.
[PHASE II] Assembly:
Every individual part has its own soldering recommendation; hence it is recommended to follow the information given in the respective datasheets. All of our SiP modules are compatible with JEDEC standard and thus every contract manufacturer should strictly follow JEDEC/IPC J-STD-020, IPC-SM-782, and IPC 7351 guidelines.
Stencil Thickness (Refer to Contract Manufacturer):
The thickness of stencil affects the amount of the paste applied on the PCB. Silicon Labs recommends stencil thickness as 4mils. However, Stencil thickness can change as per the contract manufacturer's process and equipment. Thus, the dimension of the paste mask and solder mask layers should be tried and adjusted based on the result. It is expected for many custom designs, the correct dimension can only be found out after running a few trials on the assembly line.
Moisture Sensitivity Level (MSL) rating:
Verifying moisture sensitivity level rating is very important before assembling the parts because, once the parts have been exposed to moisture for more than the rated time, the parts become susceptible to moisture which develops inside the package. If moisture gets developed inside the SiP, during assembly the moisture molecules will expand quickly into steam which will displace the internal structure and composition of the SiP, thereby destroying the electrical integrity of the parts by forming solder shorts/ solder opens and making the part nonfunctional. Hence, in such cases, the baking procedure mentioned in the JEDEC standard should be strictly followed before assembling the parts.
Most of the Silicon Labs modules are qualified for MSL-3 rating, this information can be verified at the ordering label of the received package. Every package has a bag of desiccant and a moisture sensitive strip in it. This moisture sensitive strip can be used to verify the MSL-3 rating validity.
Temperature Profile (refer JEDEC standard):
The temperature profile of the part is a very important parameter that must be taken into consideration while assembling the parts. Temperature profiles provide information such as variations in temperature and different amounts of time the part should be held at different temperatures. The profile information makes sure that the temperature is enough to wet the pads, melt the solder and form a perfect solder joint between the device and PCB. The temperature for all of the parts on the PCB has to be considered for the temperature profile, hence the contract manufacturer will have to decide a common ground for the temperature based on their experience with the particular revision of custom PCB.
Failure to reach the optimum temperature for an improper amount of time can cause assembly problems. If the temperature is too low, then there can be cold solder joints between pads of IC and PCB. Similarly, If the temperature is too high, then the part can get damaged.
All of the Silicon Labs modules are compatible with JEDEC standard. It is highly recommended to follow JEDEC/IPC J-STD-020, IPC-SM-782, and IPC 7351 guidelines to avoid any assembly issues.
No. of allowable reflow:
Sometimes a PCB must be reflowed multiple times based on the nature of the design and components used or limitations of the assembly line. During a single reflow cycle, every component is exposed to and stressed with high temperature. Exposing parts to high temperature for multiple times can damage the parts. It is always recommended to avoid more than two reflow cycles of the parts.
X-Ray to verify connections:
It is always recommended to start a small number of prototype boards and prove out the assembly process using datasheet recommendations as a starting point. X-Rays of prototype boards have proven to be very useful in determining the quality of solder and connections between the pads and PCB. This can be done under a high-quality X-ray machine that can show if there are any solder blobs, excess of solder, solder voids or solder shorts. If there are any changes required, then various board iterations should be carried out. Once the quality of the assembly is verified, then large quantity production can be started.
It is generally true that ETSI EN 300 328 allows 20 dBm RF output power in all such cases when equipment is using wide band modulations other than FHSS (Frequency Hopping Spread Spectrum). In these cases PSD (Power Spectral Density) also must be tested, which allows 10 dBm / 1 MHz.
These restrictions apply to those BLE devices, where adaptive frequency hopping is not enabled. In the case of 125 kbps, 500 kbps and 1 Mbps PHY (~1 MHz bandwidth) it means that the maximum radiated power allowed is 10 dBm. In the case of 2 Mbps PHY it is a few tenths dB more.
Based on FCC part 15.247 in the case of wideband digital modulation the output power can go up to 30 dBm and the power spectral density must be below 8 dBm / 3 KHz.
In the case of 500 kbps (coded), 1 Mbps and 2 Mbps PHY 30 dBm limitation is applied.
In the case of 125 Kbps coded PHY the device doesn’t pass the 8 dBm/ 3 KHz PSD limit with full power, thus the maximum output power allowed is 14 dBm.
Since Bluetooth stack takes the strictest regulation, thus the maximum output power is 10 dBm in those cases when AFH is not enabled (or AFH is enabled but no more than 15 channels are available). This stack limitation (10 dBm EIRP) is valid in for all PHYs and devices.
|Power Limits Without AFH|
|FCC||125 kbps coded PHY||
500 kbps, 1Mbps and 2 Mbps
|Supported by stack||10|
When adaptive frequency hopping is allowed (and at least 15 channels is available) the only one limitation is maximum 20 dBm EIRP. There isn’t any restriction for PSD.
If AFH is used, the maximum output power, which is allowed by FCC, can be 30 dBm and there isn’t any PSD limitation. FCC contains a restricted band from 2483.5 MHz to 2500 MHz and due to this in several cases power limitation is needed on the edge channels.
Considering regulations of FCC and ETSI, when AFH is applied and at least 15 channels are available, the maximum conducted output power, which is allowed by BLE stack, is 20 dBm on all channels except of on channel 37 and 38 (physical channels not logical channels) . The output power is limited to 18 dBm on channel 37 and 15.3 dBm on channel 38 in the case of all PHYs. There isn’t any limitation on channel 39, because the upper channel is only used for advertisements, so with the low duty cycle correction advertisements can be sent at full power.
|Power Limits With AFH|
|FCC||channel 37||channel 38||
all other channels
|Supported by stack||18||15.3||20|
Question: What is a STEP file?
A STEP [STandard Exchange of Product model data] file is a CAD file format defined by ISO 10303-21 to represent 3D models of components and assemblies. Since STEP files conform to the ISO standard, they are not vendor or software specific and have been adopted by the majority of ECAD and MCAD [Electronic and Mechanical Computer Aided Design] tools and systems.
STEP files are helpful to understand the physical dimensions of a particular product in a 3D domain. STEP files are also helpful to understand the area required by the part on the PCB during component placement in the mechanical assembly.
The following figure shows a sample for the preliminary STEP files for BGM13P22GA (Built-In Antenna) and BGM13P22GE (External Antenna) variants:
Question: How to obtain it?
Preliminary STEP files for our PCB modules can be obtained from Silicon Labs by contacting the Technical Support team.
There are different STEP files for different part variations. For example, the BGM13PGA (built-in antenna) STEP file is different from the BGM13PGE (external antenna) STEP file. The example highlights the difference between a Bluetooth module with a U.FL connector versus a module with a chip antenna. When requesting STEP files, please include the correct part number so that the correct file can be provided. Once received, please refer to your CAD's website or help for instructions on how to import STEP files.
To obtain a STEP file for a standard package such as QFN32, QFN48, etc, please contact our Technical Support team where you will receive a .bxl [Binary eXchange Language] file, which is a proprietary file format for vendor-neutral CAD data created by UltraLibrarian tool available on our website. Once you receive the .bxl file, please follow the instructions on the CAD/CAE webpage to generate appropriate files for your project.
The BGM121/BGM123 Blue Gecko Bluetooth® SiP Module family is targeted for applications where ultra-small size, reliable high RF performance, low-power consumption and easy application development are key requirements.
At 6.5 x 6.5 x 1.4 mm the BGM121/BGM123 module fits applications where size is a constraint. BGM121/BGM123 also integrates a high performance, ultra robust antenna, which requires minimal PCB, plastic and metal clearance. The total PCB area required by BGM121/BGM123 is only 51 mm2.
The BGM12x SiP module has an internal chip antenna which is properly tuned with a GND loop, i.e. copper clearance area, on the carrier board. For the best possible antenna performance Silicon Labs recommends to precisely follow the layout suggestions around the SiP module including the copper clearance area, as shown in the following figures.
In order to have the internal antenna tuned the GND pins 53 and 54 of BGM12x shouldn’t directly be tied together. They need to be connected to each other through the GND loop which is routed along the circumference of the copper clearance area. This GND loop makes the antenna resonate and its size determines the resonant frequency, so its layout parameters should exactly be followed as shown in the figure above. The SiP module should be placed at the board edge of the carrier PCB.
If these layout recommendations above are precisely followed on the carrier board of the SiP module then the BGM12x has the following unique features:
The impedance of the BGM12x SiP module’s built-in antenna can be fine-tuned by adjusting the copper clearance area (i.e. GND loop) on the carrier board. The figure below shows the return loss (S11) – where the resonant frequency can also be observed from the notches – of the built-in antenna with different copper clearance width. This tuning method is a unique feature for BGM12x, so the module antenna can get tuned on any custom design layout and thus exceptional RF performance can always be achieved with this SiP module.
The generally recommended copper clearance area dimensions are 5.0 x 2.2 mm on the top layer - when there isn't any metal object in the close proximity of the antenna and copper clearance area. If any metal object, e.g. coin cell battery, is mounted or attached onto the carrier board beneath the antenna area of the SiP module on the opposite layer, then the suggested GND loop dimensions are 6.2 x 2.2 mm - this assumes that the front edge of the coin cell battery is in line with the front edge of the PCB.
A more detailed guidance on the antenna tuning of the BGM12x SiP module can also be seen under the below KB article here:
The optimal board design mentioned above in point 4 refers to the generally recommended GND plane size of monopole-type antennas. Since the GND plane itself is also the part of the monopole-type antennas it is important to ensure big enough GND reference for the antenna. The smaller GND reference is ensured for any monopole-type antenna the weaker antenna performance can be expected. If the GND plane size goes below quater-wavelength then the antenna performance drops quickly.
To have the best antenna performance with BGM12x Silicon Labs recommends to use 40...50 mm wide carrier board. If the module antenna is kept tuned by following the layout recommendations, especially around the copper clearance area and GND loop, then the following curve describes the effects of the GND plane on the antenna efficiency.
RF performance when using BGM12x SiP module on a very small carrier board:
The minimum recommended board design width is 10 mm. The antenna efficiency in that case is around -12 dB. Under these conditions, the tested practical RF range with the BGM12x SiP module in office environment is about 15 meters.
The following figure shows the antenna efficiency versus board size curves for different antennas. As the curves show below the considerable antenna efficiency degradation is a general feature of any monopole-type antenna.
Training & demonstration videos:
BGM121/123 Hardware Design Guidelines: https://www.youtube.com/watch?v=5DCn7AzIyig
BGM121/123 Antenna Robustness: https://www.youtube.com/watch?v=LA2j4AXqd7Q
This article shows how tune the antenna integrated into the BGM12x with the specific use case of placing a coin-cell battery behind the SiP, therefore enabling extremely compact designs.
To understand the effects of the coin-cell battery on the antenna matching we took a BGM121 test board and placed a coin-cell in the back with a piece of blu-tak to keep it in place.
Figure 1 - BGM121 test board with coin-cell battery attached
The antenna matching can be seen in the following figures, first for the test board without battery and then after attaching the coin-cell battery.
Figure 2 - Original antenna matching for the BGM121 test board
Figure 3 - Antenna matching for BGM121 test board after attaching the coin-cell battery
Markers 1, 2 and 3 correspond to the beginning, middle, and end of the Bluetooth band. As it is visible in Figure 3 the presence of a metallic body (coin-cell) shifts the antenna tuning outside of the Bluetooth band. This is mostly due to the fact that the coin-cell is covering part of the copper clearance area and therefore reducing the antenna current loop.
To counteract this frequency shift we can extend the clearance area simply by scrapping away the ground layer as shown in Figure 4. Due to the the underlying uncertainty on how much it needs to be extended we’ll just extend it about 50% more as it is then easier to re-add a metal plane in order to fine-tune the clearance area.
Figure 4 - Extending the copper clearance area
The antenna matching of the modified board is show in the next figure.
Figure 5 - Antenna matching after extending the copper clearance area
The matching is still off-band but this time it is towards the lower frequencies which can be compensated by reducing the copper clearance. To reduce the copper clearance we simply cover it with a piece of metal (a shield from one of our modules in this specific case) until we get the correct matching as shown in the next figure.
Figure 6 - Reducing the copper clearance area to fine tune antenna matching
The antenna matching is now back into the Bluetooth band and very close to the original design.
Figure 7 - Antenna matching after reducing size of the copper clearance area
The presence of metal very near to the BGM12x can have a negative impact on the antenna matching. However, it is easy to compensate the effect by adjusting the size of the copper clearance area to bring the antenna matching back into the Bluetooth band and ensure the best RF performance for your design.