we use wds gui ver 184.108.40.206 and build ver 2016-12-16.
from above wds, we can communicate each other with two si4463 pcb board after extracting config parameter for data rate 2400bps.
after ok with 2400bps, we change only data rate from 2400bps to 1200bps on wds and extract header file for config parameter.
build is no problem and transmitter look like ok using spectrum analyzer but can not comunicate each other.
so far, we have not solved this problem.
Hi. I poll modum status often to get the current RSSI (background noise). I use this to set the RSSI threshold above background noise for clear channel assesment. Until preamble detection, I have no way of knowing if the receiver is receiving a preamble. If I polled modum status during this initial period of packet reception, would it effect the sensitivity of the receiver? Worst case, causing the preamble detect to be missed?
IS THERE AN OPPORTUNITY IN RAIL 2.0, WITH MODULATION OF 4FSK, ORGANIZE DATA RECEIPT IN INFINITE MODE?
If there is an opportunity, what template should I use to implement it?
I used interrupts. When send packet, ipksent bit is set. nIRQ pin also in high after sent packet. But after reading status regarding 3 & 4, that bit is not cleared. nIRQ pin is high. Due to ipksent bit set, if I receive data from sender, it sends data and collusion occurs. Or sometime it sends data 2/3 times. Any solution pl?
And of course - rail's callbacks must be static members, since they are interrupts in fact
I hope I can switch the state of SI4463 on interrupt, I turn on the transmit complete interrupt and receive complete interrupt. However, getting the SI4463 current interrupt flag in response to an interrupted program is not the interrupt flag I set.
Hi, I have a SI1064DK,
When I download the code throght the WDS directly and without using the IDE the code works fine. But As I open the IDE and without changing the code, after downloading it, the MCU resets during executing the function "vRadio_Init () " . Kindly help if you know the reason. As I said I don't change anything with the code.
FG series chips support 2.4G and SUB1G, why it only supports proprietary protocols? The MG series also has 2.4G and SUB1G but it can support multiple protocols.
The RTCC seem’s to drift after or while sleeping in EM2.
Using BLE stack ( V220.127.116.11 ) in a custom IAR project. I know RTCC is used by the BLE stack. so I’m just reading the RTCC register.
In my project, the LDMA automatically record the RTCC->CNT register on the falling edge of a GPIO ( through a dedicated PRS channel ). ( I am not using the NCP UART mode, so I have full access to the LDMA )
This is working correctly, but sometimes the RTCC capture is incorrect and seem’s to drift, permanently.
If I disable sleep mode (SLEEP_SleepBlockBegin(sleepEM2); ), then everything is correct…
To test, I set a 400 ms pulse on the GPIO, and check every 2 sec, all RTC value captured by the DMA :
 uiCounterVal=13172 (401.977539 ms) [ 18555361 18542189 ]
 uiCounterVal=9879 (301.483154 ms) [ 18565240 18555361 ] RTCC VALUE IS INCORRECT !!!!!
 uiCounterVal=13172 (401.977539 ms) [ 18578412 18565240 ]
 uiCounterVal=13172 (401.977539 ms) [ 18591584 18578412 ]
RTCC->CNT value :
18542189 first RTCC->CNT capture
18555361 delta with previous RTCC->CNT = 13172 => 400 ms OK
18565240 delta = 9879 => 300 ms ( RTCC VALUE IS INCORRECT !!!!! )
18591584 delta = 13172 => 400 ms OK ( but are now desynchronized, it’s like if the RTCC has lost 100 ms … strange ! )
The LFXO clock is running correctly ( deviated on a GPIO ( with CMU ) and checked on oscilloscope )
Is the RTCC still running while going in EM2 sleep by BLE stack ?
Is there any problem while accessing the RTCC->CNT register with LDMA while sleeping ?