1. Clarify to yourself what the specific issue is.
2. Apply basic troubleshooting:
3. Consult the datasheets and reference manuals. Sources include:
4. Search to see if someone has asked the same question already.
5. If you use custom hardware, try to reproduce the issue on a Silicon Labs kit
6. If you have a big firmware project, try to reproduce the issue on one of the Silicon Labs examples with minimal modification
7. If you have a radio configuration problem, try to reproduce it with RAILTest or WDS
8. Include the relevant parts of your development setup in the problem description. Examples include:
9. Include steps to reproduce the problem or specific conditions the problem occurs in.
10. Be patient and avoid making duplicates of your question.
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Hi, I'm looking at looking at figure 3: of AN629. All the components are 0402. I'm designing for 120Mhz and need large inductance, at least for LC. The biggest I can get is 470nH using 0603 LQW series.
I have used all 0603 inductors in my layout for the TX and RX networks, thinking that the higher Q will be a good thing. In turn I have used 0603 caps as well, as components of the same size marry better on the layout. Of course the layout uses a greater area because of the larger component sizes, and will introduce more stray capacitance. (4 layer board)
Would you recommend against using 0603 components unnecessarily? Will it have a negative effect on performance? Perhaps the cross talk between inductors is likely to be greater? Or do you think the higher Q will out weigh other degrading factors?
I am using BRD4164 and flex sdk 2.7.6. i have created mac_device example and enabled NVM3 plugin according to AN1153. All the necessary files where successfully generated.
After which i have used NVM3 according to API document example with same parameters but i am facing error in nvm3_open() as ECODE_NVM3_ERR_ALIGNMENT_INVALID. i am not able to recognise the reason of such error.
i request you to help me resolve it.
Also i have done setup of NVM3 in RAIL library in which also i am facing similar issue of nvm2_open() in which i get error as ECODE_NVM3_ERR_OPENED_WITH_OTHER_PARAMETERS. can you please help me with this also.
Hi all, I am making a matching circuit for Si4432 RX differential LNA operating at 403 MHz,
1) What are the best RX LNA matching parameters for Si4432 with operating freq. 403 MHz?
2) Where can I get differential LNA input impedance of Si4432 at 403 MHz (i.e. rlna and clna parallel impedance values required) and calculate the matching parameters myself?
I'm now designing a 433M wireless system with Si4438.
I've read some recommand documents from Silabs for TX/RX matching.Details of RX LNA matching, documents for Si446x or Si443x can be found, the examples are Si4463 & si4432.
As i know, the RX LNA matching circuits are different with "IC Differential LNA Input Impedance", now my questions are :
1. Whether the RX matching circuit of Si4463/Si4432 is suitable for Si4438?
2. If not, where can i get the best RX LNA matching parameters for Si4438?
3. If not, where can i get the "Differential LNA Input Impedance" of Si4438 and calculate the parameters by myself?
EFR32MG13P732F12GM48 on a Wireless development board.
I have a custom application with the SI provided Apploader. Apploader is at 0x0000 0000 and my application follows on the next flash page.
I am trying to activate the AppLoader from the user application.
If I use the soc-empty example:
Using gecko_cmd_system_reset(2) -> reboots to apploader
I want to be able to reset into apploader without using the functions as my custom application doesn't have the bluetooth stack in it and therefore doesn't have that function call.
I tried to write my own reset function using the BTL_RESET cases but it doesn't work:
It just reboots to the normal application and doesn't run appLoader.
What values do I need to pass it? What magic is in the gecko_cmd_reset(2) that the below doesn't use?
// Set reset reason to bootloader entry
BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (RAM_MEM_BASE);
resetCause->reason = BOOTLOADER_RESET_REASON_OTAVALID;
resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID;
// Clear reset cause
RMU->CMD = RMU_CMD_RCCLR;
// Request a FULL reset using the Core System Reset Mode
RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_FULL;
// Trigger a software system reset
I have been developing on the Si4468 RF project.
The center frequency is 284 MHz, Channel width is 50 kHz, 2GFSK modulation, Standard packet (7 bytes)
After measured, The set-up Tx signal is not good, has much noise.
In 9600 bps , 9600 Hz deviation, The RF waveform and RF setup file are as below.
In 19200 sps , 19200 Hz deviation, The RF waveform and RF setup file is as below.
The waveform of 19200 sps is worse than that of 9600 sps.
In hardware ,
The schematic is referenced the SI4463/68 Class-E Switched 27dBm matching circuits,
To do 20 dBm output power, We removed power amp components, and replace passive component values.
How should I get good Tx signal?
I am attempting to design a custom PCB that has the debug adapter on it used to connect to WDS3 over USB. I am designing for both the Si4362 and the Si4012.
I found schematics for the wireless motherboard (MSC-WMB930) that can support debugging both the Si4362 (4362-PRXB915) and the Si4012 (4012-PSC10B915). However, from the schematics I have a couple of questions on how actually to implement the debugging features.
First, I notice that both of the RF Pico boards have EEPROMs on them that contain identification information required for WDS3 to detect which device it is talking to. Are the contents of these EEPROMs available for download anywhere?
Second, I see on page two of the wireless motherboard schematic that there are two MCUs (U6 connected to the USB port, and U10 connected to U6). From another form post I saw that the one connected to USB is pre-programmed, however the other one (U10) is not. Is either a compiled image or source code for the chip marked U10 on the MSC-WMB930 motherboard available, or is that chip even necessary for connection to WDS3?
Lastly, as I understand it, the MCU Pico board runs the end-user's code, however, the SPI bus from the Si4362 Pico board only goes to the MCU Pico board, not to the debug interface. However, the Si4012 uses I2C, which goes to the second (U10) MCU in the debug interface. Does the Si4362 require three MCUs and the Si4012 require two MCUs to connect to WDS3?
Hi, we need to develop an industrial application with more than 150 nodes.
Each nodes is solenoid actuator and a sensor
There is no concurrent actuation of those devices, in fact I've to connect sequentially to each of them at startup, than activate some of them during the process and read the sensor data.
The data rate is very slow, and I've not power supply problems (I've a permanent supply rail).
We need to design the entire solution, the slaves devices (actuator and sensor) and the central master unit that manage the operations.
The single slave units has to be repleceable, if possibile without using a "dip switch" like addressing, so we have to implement a dinamic addressing of new devices (using a push button for example to put them in "addressing mode"). I think a Star network will be simpler.
What is the Silabs suggestion to design this product, for slaves and central unit ? BLE, or proprietary stack?
We would like to use some certified module with integrated antenna, 2.4GHz .
Thanks in advance
Hi, I need to design a custom board using EFR32MG13P733F512GM48 Sub-GHz capabilities but I don't need the 2.4GHz part (pin 19 and pin 20 related to). Can I left these pins unconnected? Should I take into account others pins for disabling the 2.4GHz radio?
When a power failure occurs for short period, sometimes RX_RAW_DATA signal from GPIO1 of Si4362 stops due to the internal register corruption. In this case, a host MCU does not detect the power failure and therefore does not take any recovery action to initialize Si4362.
According to Si4362-C datasheet, VRRH (Voltage for successful POR) is specified as 90%xVDD. Does this mean that 90%x3.3V=2.97V and if VDD drops below 2.97V, Si4362 internal register can be corrupted? Does the host MCU need to detect the power failure with a threshold of 2.75V? Is there any alternative way to detect a power failure on Si4362?
Could you please provide an example of how to use RAIL_ConfigSleep(), RAIL_Sleep() and RAIL_Wake().
I would like to add it to the soc-light-rail-dmp example.
Could you also provide some explanations on the SleepAndSyncProtimer() function. Is it part of the stack? I can't find it's implementation or description.
I have an application based on SI4463 chip. It works about 1 second, then CPU is halted unless it wakes-up and starts main loop again.
When I powerup the device, and configure si4463 by power_up command etc. everything works fine, and I have about 7mA consuming.
Then shutdown happens, main CPU is halted, shutdown pin hold high (0mA consuming).
But after CPU wakes up, and makes all the same commands (power_up, etc.) the consuming becames two times higher (about 14mA).
It seems that si4463 was not fully powered down by shutdown pin and then works in the other mode.
How this can happen? And is there any solution in such case?
I am using device EFR32FG12P231F1024GM48 custom board and Flex SDK v2.7.6. I have imported RAIL example Simple TRX with FIFO.
i require to use SIM EEPROM for my proprietary SDK but as per plugin to enable iit is under Connect . But still when i enable SIM EEPROM it requires HAL library even though HAL is enabled into RAIL library. Also when enable HAL libary of Connect the dependency of other plugin arrives.
i request you to provide me a way in which i will be able to use SIM EEPROM under RAIL library.
I have generated the WDS settings for 4GFSK 100 kbps and I am able to transmit and receive. But sometimes the bit error happens and the receiver is getting the wrong data.
Below are the data received on receiver for CRC error
RX: len=500: 0 1 75 7 6b da f3 2f 5f b8 f4 d3 7e 45 a0 c3 ea b6 6f 60 5b ec ee 0 8d 8c 2e 5d 52 33 e5 18 47 a a6 44 8f eb b2 c cf 7 95 dc 94 e5 25 e5 f5 4a f2 ea 8f e7 e8 33 b e 40 a0 ac 69 ce 32 8e 13 40 83 7 c9 70 b ae 39 17 83 1 e4 6f e9 8a f3 89 bf 67 b1 a4 14 46 4a dd 1b 10 9d d8 26 dd e1 4c cd d6 4d 35 c4 ad 85 d2 fd ea 27 3a 30 b4 40 be d5 76 dc fd 9b 1d 2 27 ad a8 b4 35 cf 3b 44 15 11 34 4 ff 1b eb bd 19 41 7c e0 d0 c3 88 67 91 40 15 47 f c4 ea d2 93 81 99 a6 af 5f 35 cd 65 6b 33 54 a9 66 a4 f 4d fb 92 ac c6 e6 33 ea d a9 11 b3 28 b8 c6 b0 38 1a 38 40 59 bf 68 9f c5 df 7d b4 45 dc 7b 2b a4 ce e 74 aa ed 4 b1 74 3b 58 1b 26 0 de 35 2f 6d 3b cd f4 3e 13 fb 45 76 21 b4 5d 68 4 a3 b7 64 f6 5 b3 3a ab c6 46 de a 8a fa b1 2e fe c0 42 fd 17 6e fd a4 73 5 65 d8 f5 2d 41 ba f2 d1 70 47 a6 c1 d4 b4 69 62 55 ee e8 2 93 8e 28 5f 5c 31 e3 1a 39 8 a0 46 81 e9 b4 e d1 5 93 de 9a e7 23 e7 cb 48 f4 e8 81 e5 ee 31 15 c 46 a2 a2 6b c8 30 70 11 46 81 9 cb 76 9 b0 3b 11 81 f e6 69 eb b4 f1 8f bd 69 b3 a2 16 58 48 db 19 1e 9f de 24 a3 e3 4a cf d8 4f 33 c6 b3 87 d4 ff e4 25 3c 32 8a 42 b8 d7 78 de fb 99 3 0 21 af a6 b6 33 cc c5 46 13 13 3a 6 f9 19 f5 bf 1f 43 72 e2 d6 c1 b6 65 97 42 1b 45 9 c6 f4 d0 95 83 97 a4 a9 5d 4b cf 63 69 3d 56 af 64 ba d 4b f9 9c ae c0 e4 d e8 b ab 1f b1 2e ba d8 b2 3e 18 36 42 5f bd 96 9d c3 dd 73 b6 43 de 65 29 a2 cc 0 76 ac ef 3a b3 72 39 56 19 20 2 c0 37 29 6f 35 cf f2 3c 6d f9 43 74 2f b6 5b 6a 1a a1 b1 66 f8 7 b5 38 95 c4 40 dc 4 ***CRC_ERROR*** CRC=0x611c292d
Actually data which is sent is from 00-FF and it repeats for 500 bytes.
I will attach the register setting for the 4GFSK. There are few registers which have changed from 2GFSK to 4GFSK which has been incorporated in the code.
Also attaching 2GFSK setting for refernce. The 4fsk notes attachment list the register that should be set for 4GFSK. Also I am not using the inbuilt crc on chip this is calculated in our code. I have observed the SPI lines on receiver and its the receiver which is pumping wrong data on SPI
If I am missing anything please let us know