Hi,

I encountered a problem when I followed the instructions of the "qsg138-flex-efr32.pdf" to work with Connect Host/NCP example. The problems is:
========
I copied whole "./SimplicityStudio/v4/developer" folder and "./SimplicityStudio/v4_workspace/wire-replacement-host" to Raspberry Pi 3. The compilation is good, however, the console doesn't show "Network Up" when I executed "start-master 0",

$sudo build-wire-replacement-host/wire-replacement-host-unix-host-app -u /dev/ttyACM0
wire-replacement-host> start-master 0
CSP command timed out: EMBER_SET_SECURITY_KEY_COMMAND_IDENTIFIER
CSP command timed out: EMBER_FORM_NETWORK_COMMAND_IDENTIFIER
CSP command timed out: EMBER_PERMIT_JOINING_COMMAND_IDENTIFIER
========

The EVM is EFR32MG12 2.4GHz 19dB (BRD4161A Rev A02)

Could you do a favor to see how to fix the problem?

Thanks.

Hi,

I have both your Si4455 EVB board and a third party module including Si4455 from Zeta.

I can successfully configure and send TX packets using your EVB board which is controlled by my custom ARM board but could not have managed the same thing with Zeta's board.

Although it successfully replies as CTS = 0xFF to 0x44 command, it always returns other parameters as 0x00 to any read command such as 0x01. Moreover it pulls low the nIRQ pin after the first 8 bytes of the PATCH. But in working Silabs' EVB, nIRQ never be low.

In both boards Si4455 marking is 455A. But as I understand from the datasheets it is written as 445A for both revisions B1A and C2A. How can I distinguish them?

Here below is marking:

Working Silabs' EVB: 455A, C4RU, 536

Zeta's Module: 455A, BFCS, 619

In the response of Silabs' EVB to 0x01 command I can read 0x44 0x55 as device ID but for Zeta's board all return bytes are 0x00.

Perhaps Zeta's board is B1A firmware vesion?

Best regards,

Bora

Hi,

I am currently working with the EFR32FG14 series starter kit. The whole application is controlled by a DSP. What are the possible ways to achieve  my requirement ? I need to receive data in the transceiver and have to send it to the master after interrupting it.

Thank you in advance for any help you can provide.

Hi,

I am currently using EFR32FG14 series transceiver for my application. How could we test the SPI communication of the transceiver with a master device ? Is there any supporting documents or application notes from SiLABs ?

Hi, 

I am a beginner in this series of Transceivers. In the simple_trx example provided by SiLABs, how could we monitor the received data. The example is done for blinking an LED.

Has anyone configured the EFR32's data whitening capability to be compatible with a CC1101? The CC1101 uses a PN9 polynomial with an initial value of all 1's and the exact same algorithm as mentioned here:

http://www.silabs.com/Support%20Documents/TechnicalDocs/AN592.pdf

I've been using the Radio Configuration setup in the simple_trx demo but can't get the whitening feature to work with my existing CC1101. I've tried multiple combinations of Whitening Output Bit and Whitening Seed yet nothing comes out correctly whitened. The seed field is also 16 bits, so I'm not sure what to put there as I only need 9 of them. Is this whitening hardware\firmware documented somewhere?

Hello, everyone! I am a newer for wireless communication. I downloaded the WDS3 from the silabs and installed it.I imported all the *.c and *.h in the path "SiliconLabs\WDS3\DemoExample\Si446x_BidirectionalPacket\src" to sourceinsight(source code editor), but I can't find some variables' definition. such as Si446xCmd, Pro2Cmd[], pRadioConfiguration and so on. I tried other demo projects, still not find them. Can anyone tell me why? thanks in advance! 

Hi,

It is disappointing that I can not configure the RFIC to autonomously return to sleep on "Hop Wrap". 

Consider LDC RX without hopping for a moment. The LDC period, i.e. the period in which the RFIC is awake and in RX mode, has to be long enough for a 'Preamble Detect', with DSA that is 16Tb or more. However, if the DSA returns a 'No Signal Detect' after 4Tb, the RFIC can return to sleep.  The RFIC is not awake for the entire LCD period, reducing the duty cycle by a factor of four which saves a lot of current.

My application uses LDC RX and auto hops through five channels during the LDC period. Worst case scenario is that channel number 5 is active and the receiver has to dwell on four channels for a 'No Signal Detect' of 4Tb, and on the fifth channel for a 'Preamble Detect" of 16Tb. The LDC period has to be at least 32Tb.  If no signal is present on any of the channels, ideally the receiver would hop through the five channels, dwelling on each for 4Tb (No Signal Detect) and then return to sleep after the hop table wraps. This way the RFIC would only be awake for 20Tb per LDC period. But instead the hop table wraps and the receiver continues to hop through channels it has already checked until the full LDC period expires. This is a missed opportunity for a 50% saving in current.

Hi everybody!

I'm using Simplicity Studio and the RAIL API to communicate two Blue Gecko boards (EFR32BG1P232F256GM48 - BRD4100A Rev. B01) each other in proprietary mode. The boards are connected by wire through their UFL ports, and each board is isolated in a Faraday's cage to avoid interferences. The aim is to obtain BER vs Rx power curves at the ISM 2.4 GHz frequency band. In fact, I have obtained yet correct curves for 2GFSK modulation working with constant Tx power and digital attenuators to modify the Rx power.

However, I'm having bit-corruption and lost frame issues in the receiver at unexpected Rx power levels (for example -50dBm) when I use any modulation different to 2GFSK (for example 4GFSK and MSK). I'm following the instructions of the document "AN971: EFR32 Radio Configurator Guide" to choose properly the bitrate and the rest parameters. As preamble and syncword I'm using the default values provided by the API (preamble = 0x‭5555555555‬; syncword = 0xF68D ) because they are 2FSK-coded always as far as I know.

¿Does anyone know what could be the origin of the problem? ¿Should I use different preamble and syncword? ¿Could the hardware not be prepared to work at 2.4GHz band in any different modulation from 2FSK?

Thanks in advance!

I am trying to use the SI4455 with a legacy protocol. To do this I need answers to a few questions.

In variable length mode, it is possible to add an offset to the length? ie if the length byte in the packet is 10, can the SI4455 set the RX length to be 10  + 2 (offset) = 12 bytes for that packet?

Can the SI4455 packet length byte location be set to the second byte after the sync bytes rather than the first byte?

If a packet is longer than the number of bytes specified in the variable length byte, is there any way to read the extra bytes? It seems the packet handler stops loading to the RX FIFO once it reaches the specified number of bytes.

Is it possible to modify the values of individual registers in the SI4455? There does not seem to be an API for this or a description of what the registers are.

Hi, I have a question.

Does Connect have RFSENSE support or something? I need to wake the MCU with radio frequency detection.

Have anyone encountered auto reboot issue on Flex 2.0 Connect SOC examples?

I built several Connect examples such as "Sensor"/"MAC Mode Device"/"Wire-Replacement" and run on EVK brd4151A, all these examples will auto-reboot after flash finished. The serial printing show error message as below: 

[ASSERT:lower-mac-rail-802.15.4.c:209]
Reset info: 0x07 (CRS)
Extended reset info: 0x0701 (AST)
Thread mode using main stack (20006360 to 20006CC8), SP = 20006C30
616 bytes used (26%) in main stack (out of 2408 bytes total)
No interrupts active
Reset cause: Assert lower-mac-rail-802.15.4.c:209
R0 = 00002BB8, R1 = 000000D1, R2 = 00000000, R3 = 00000002
R4 = 20007B14, R5 = 00002BB8, R6 = 2000709C, R7 = 00000000
R8 = 00000000, R9 = 00000000, R10 = 00000000, R11 = 00000000
R12 = 80000000, R13(LR) = FFFFFFF9, MSP = 20006C30, PSP = 00000000
PC = 00001A14, xPSR = 41000000, MSP used = 00000268, PSP used = 00000000
CSTACK bottom = 20006360, ICSR = 00000806, SHCSR = 00070008, INT_ACTIVE0 = 00000000
INT_ACTIVE1 = 00000000, CFSR = 00010000, HFSR = 00000000, DFSR = 00000000
MMAR/BFAR = E000ED34, AFSR = 00000000, Ret0 = 0000216F, Ret1 = 00003FBF
Ret2 = 000081F7, Ret3 = 0000539B, Ret4 = 0000544B, Ret5 = 00013A05
Dat0 = 00002BB8, Dat1 = 000000D1

Anyone know how to fix this or have the source code of lower-mac-rail-802.15.4.c? Please teach me...

Hi, I've got a wireless product that has been using the EFR32MG1P232F256GM48 processor and RAIL.  I've recently had some boards updated to use the EFR32MG13P732F512IM48.  In code I updated the rail driver to "librail_efr32xg13_iar_release.a" version 1.6, updated the microcontroller selection, drivers, etc.  I'm using emlib version 5.2.1.  Everything builds and loads onto the chip correctly, but the new microcontroller won't transmit.  Commands to the rail library are not returning errors, but transmit is not working at none of the transmit or recieve callbacks are occurring.

My question: Does the EFRMG13P require anything different than the EFRMG1P in order to get it to transmit? Is RAIL version 1.6 and emlib version 5.2.1 alright or do I need something newer?

Thanks for any help,

Steve 

Hello,

We are having problems with ezradio driver and proposed  "SLWSTK6220A_ezradio_simple_trx" example when using Half duplex mode (GLOBAL_CONFIG:FIFO_MODE = 1 property), that is, when 64 byte Tx/Rx FIFOs are joined into a single shared 129 byte FIFO. We believe that this issue may be caused because the proposed example / ezradio driver by Silabs does not consider this case. Therefore, Tx/Rx operations overlap each other without securely accessing the (newly) shared resource.

We are using the following HW (SLWSTK6220A):
- BRD4001A (Main board) x2
- EZR32WG330F256R60G (BRD4502C) 868Mhz 13dBm board x2

We are using the following IDE:
-Simplicity Studio v4

Additional development information is supplied:
  32 bit MCU SDK                    5.2.1.0                    com.silabs.sdk.exx32.v5.2.feature.feature.group    Silicon Labs
  EZR32 Part Support                4.0.4.201703070028-48    com.silabs.metadata.ezr32.feature.feature.group    Silicon Labs
  Generic Example Support            4.0.1.201610211448-18    com.silabs.metadata.examples.feature.feature.group    Silicon Labs
  GNU ARM Toolchain (v4.9.2015.q3)    4.9.2015.q3    com.silabs.ss.toolchain.gnu.arm.4.9.2015.q3.feature.feature.group    Silicon Labs

Current test setup:
 - Node Station: One main board + ezr32wg330 radio board
    -> Tx every 1 second (simulating a sensor read)
    -> Uses EZRadioPro LDC (Low Duty Cycle), to listen messages from Base station.  Listen period=1second, listentime=25ms
    
 - Base Station: Second main board +  ezr32wg330 radio board
    -> Tx every 80ms (simulating a base-to-node sensor configuration command -in a burst to fall within listen window)
 
Issue found:

Our test considers that the Tx and Rx packets are known, identical and always the same. Each time the ezradio generates an Rx interrupt, we compare the FIFO contents with our expected known packet. The program is run in an infinite loop. It is observed that spontaneously from time to time (approximately at maximum 1-2 minutes of starting the infinite loop), the contents of the FIFO are not as expected. The ezradio CRC error callback is not called, so the packet is considered as valid by the transceiver. However, the packet is obviously not correct because it differs from the known packet.

Here we arrive at the conclusion that some issue must be happening at low level ezradiopro radio driver. We believe that since the provided example considers independent Tx / Rx 64 byte FIFOs, when switching to a 129 byte shared FIFO it does not properly manage the shared resource.

Node Fw console outputs:

"No Tx possible": The console prints that when the Tx busy flag is kept set and not properly reset from radio sent callback function

"ERROR": The console prints that when checks the content of the Rx buffer read from the transceiver fifo and checked with the data we expect to receive from base project.

Notice that we have limited the printf in the system to not interfere with the main radio process being carried by the system, which we consider, must be kept clean.

As we cannot rely on this code to retrieve valid data from the shared fifo every time a radio packet is received, we ask for some guidance or example snippet code to properly manage the half-duplex FIFO.

Thanks for your time and help

Hello,

We are new with Silabs products and ARM MCU.

We are students and we must realize a prototype for a company but we don't know how to create a new project.

The solutions I have tried is :
 

New project -> Silicon Labs AppBuilder Project -> Silicon Labs Flex SDK -> Start with a blank application -> Plugins: RAIL Common -> Generate Many errors with missing files 

What is the easiest way to create a new application ?

IDE : Simplicity Studio V4

SoC: EFR32FG12P431F1024GM48