How do I setup Custom MFG Tokens?
The first thing to do when setting you custom manufacturing tokens depends on whether or not you want to use a custom token header file. It does not matter if you choose to use a custom header file, or if you modify the generated token header file as it will be the only one used in the project. However, if you do decide to use your own custom header file you must define APPLICATION_MFG_TOKEN_HEADER to be your custom header file in your IAR preprocessor. When creating a custom token header file, token.h has helpful instructions. It is also important not to use inclusion guards (#ifndef/#define) in your application header files as the token reference scheme will not work with them. (If you are adding the define to App Builder, make sure to select the -D option).
Please note that if you do decide to modify the generated file you will need to be very careful not to overwrite it once modified. The main concern of it being overwritten is when you regenerate your project. At that point it will, by default, have the tokens file selected as being overwritten. Make sure to deselect it any time if you have made edits to the file that you want to keep.
General token definition found in token.h:
* The most general format of a token definition is: * * @code * #define CREATOR_name 16bit_value * #define NVM3KEY_name 20bit_value * #ifdef DEFINETYPES * typedef data_type type * #endif * #ifdef DEFINETOKENS * DEFINE_*_TOKEN(name, type, ... ,defaults) * #endif * @endcode
I see high radiated harmonics with Si4x6x radio chips with even good conducted results. What can be the main source of the harmonic radiation?
If the conducted spectrum looks good in terms of output power at the fundamental and at the harmonics too the harmonic content of radiation is likely not radiated via the antenna. In that case the VDD lines can be suspicious, since the harmonic content (generated in the switched mode PA) can go through the choke inductor (through its parasitic capacitance at the higher frequencies) and can be radiated out by the VDD traces. In that case the harmonic filtering of those VDD traces becomes more important and suggested.
Moreover, traces connected to the SDN, GPIO 2 and 3 pins might be the main radiators of the unwanted harmonics, so the additional filtering of those traces is also recommended - typically with series blocking inductors placed close to the chip pins that have SRF at the critical harmonic frequency.
I see high radiated harmonics with Si4x3x and Si10xx radio chips with even good conducted spectrum. What can be the main source of the harmonic radiation?
If the conducted spectrum looks good in terms of output power at the fundamental and at the harmonics too the harmonic content of radiation is likely not radiated via the antenna. In that case the VDD lines can be suspicious, since the harmonic content (generated in the switched mode PA) can easily go through the choke inductor (through its parasitic capacitance at the higher frequencies) and can be radiated out by the VDD traces. In that case the harmonic filtering of those VDD traces becomes more important and suggested.
What are the main design differences between the different matching network types for Si4x6x-based radios?
This is a conventional complex conjugate matching. The required differential balun matching impedance should be the complex conjugate of the differential RX input impedance of the chip. The single ended side impedance of the matching balun network is 50 ohm.
Details in AN643 app note.
a) Class-E (CLE)
Not a conventional matching procedure. The transistor should be only considered as a switch (switched mode PA). Here, the goal is to get matched for the desired output waveform (Class-E type voltage and current waveform). For this the required load impedance can be calculated what depends on the internal parallel shunt capacitance and frequency. The output power depends on the frequency, shunt capacitance and supply voltage. The shunt capacitance is given, included inside the chip and has different values for the Si4460/61/63/64 RFICs from 1.25 to 2.5pF. At a given frequency the maximum achievable output power is larger if the shunt capacitance and/or supply voltage are also larger. With a given shunt capacitance the maximum achievable output power is larger if the frequency and/or supply voltage are also larger. At a given frequency the different RFIC types (Si4460/1/3-4, i.e. different shunt capacitance) need different matching network values. Advantage is the very good power efficiency (i.e. low current consumption). Disadvantages are the quite strong VDD dependency in the output power level and the relatively higher voltage swing at the output TX pin.
b) Square-Wave (SQW)
Not a conventional matching procedure. The transistor should be only considered as a switch (switched mode PA). Here, the goal is to get matched for the desired - square wave - output waveform. For this it is required to load the chip TX output with a fixed impedance in wide-band. We have to ensure the same impedance for the fundamental and even for the harmonics to get the square wave output waveform. The harmonic trap parallel resonant circuit with loaded Z ohm impedance ensures the required termination for the harmonics, meanwhile shows high impedance for the fundamental what is driven forward via the filtering section what shows the required Z impedance. So, in this way the harmonics are filtered and terminated by Z ohm and the fundamental is also terminated with Z ohm by the filter. Z is typically 50 ohm. The matching values only depend on the frequency. It has good efficiency, lower voltage swing and more acceptable VDD dependency compared to Class-E.
c) Switched-current (SWC)
This is a more conventional PA matching procedure. The TX output stage can be imagined as a current generator what pumps fixed current to the load. The output power based on the amount of the current can be handled by setting the load impedance. At a given current the output power is higher if the load impedance is higher. The limitation here is the maximum allowed voltage swing at the output TX pin tolerated by the chip. At a fixed output power level the best efficiency (i.e. lowest current consumption) can be achieved with the largest load impedance while the voltage swing has an acceptable value at the TX output (do not cause degradation). Reducing the load impedance value the efficiency becomes worse, but the matching will become more robust against the VDD dependency.
TX matching procedure details can be found in our AN627/648 app notes.