How the 32.768kHz crystal is suggested to be used?
1. One of the pins of the crystal needs to be connected to a GPIO, but where shall I connect the second pin?
2. Is a capacitor required (if so what value) for the crystal operation?
A1: The crystal has to be connected between GPIO_0 and GND! Please find our reference design, with the schematic and the xtal setup (Q2).
A2. The capactitor is not required for normal operation. The placeholder (C5, N.F. - not fitted) is on the board for debug purposes. Using a 0.5pF series capacitor the crystal operation can be monitored without influencing its operation.
Here is some help from the datasheet page 56:
'A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h 'Operating
& Function Control 1', GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to
this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be
connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set,
all internal functions such as WUT,micro-controller clock, and LDC mode will use the 32 kHz XTAL and not the
32 kHz RC oscillator.'
If the LDETB signal cannot be used as a PLL settling indicator, what approach should one take?
As noted in RF Synthesizer Knowledge Base article LDETB signal as PLL settling indicator (90292), the LDETB signal should not be solely relied on as a PLL settling indicator. This is because it also serves to indicate the PLL is about to lose lock due to temperature drift. Therefore LDETB can be asserted before the PLL has sufficiently settled in an application, e.g. to within 0.1 ppm of the settled final frequency.
The best approach is to allow for the maximum settling time and then check LDETB. The Si4133 datasheet (Rev. 1.61 as of this writing) for example gives the following guidance regarding settling time:
The settling time for the PLL is directly proportional to its phase detector update period TΦ (TΦ equals 1/fΦ). A typical transient response is shown in Figure 6 on page 11. During the first 13 update periods the Si4133 executes the self-tuning algorithm. From then on the PLL controls the output frequency. Because of the unique architecture of the Si4133 PLLs, the time required to settle the output frequency to 0.1 ppm error is automatically 25 update periods. The total time after powerup or a change in programmed frequency until the synthesized frequency is settled—including time for self-tuning—is approximately 40 update periods.
Note: The settling time analysis holds for RF1 fΦ > 500 kHz.
Testing should be employed to confirm the worst case settling time for the worst case update rate in any particular application.
What are the recommended 30 MHz XTAL specs (ESR, load capacitance, etc.) for Si443x radios? Is there any recommended part number?
Our recommendation is ESR < 50 ohms, load capacitance 10pF. In our Si443x reference designs we currently use a crystal from Tai-Saw Technology, TZ1430A.