How can I design a dipole antenna with good harmonic suppression?
Answer
Designing a printed dipole antenna directly to differential chip RF outputs makes always sense. This is mainly driven by cost considerations since the balun function can be eliminated from the RF front-end in this way. On the other hand, the ground plane (which size is critical in many cases) does not affect the performance of the differential-type antennas.
But, the filtering becomes more challenging on dipole antennas and a result of this high radiated harmonic levels might be observed. To fix this or to achieve better harmonic suppression the following filtering and matching method is suggested.
- Dipole antenna can be matched by its total length and a parallel capacitor (C_par) between its two ports
- The required parallel capacitance between the dipole ports (C_par) can be divided into two parts: C_odd and C_even
- One capacitor with C_odd value is suggested to be placed between the dipole ports
- Two capacitors with C_even values are suggested to be placed from each dipole ports to GND
- The C_odd capacitor can be tuned to become a good filter at one of the odd harmonics
- The C_even capacitors can be tuned to become good filters at one of the even harmonics
- Meanwhile, the total parallel capacitance (C_par) required between the dipole ports should be C_par = C_odd + [C_even*C_even / (C_even+C_even)] = C_odd + C_even/2. Since, the two C_even capacitors are in series connection with each other (through the common GND connection) and they are in parallel connection with C_odd.
Here is an example printed dipole antenna design for 2.4 GHz.
- 22nH is an RF choke inductor (shows high impedance at the fundamental)
- 3.3nH is a parallel inductor between the RF output pins to match the RF chip output
- 1.2pF is the C_odd capacitor
- 2x2.4pF are the C_even capacitors
- SMD1206 12pF is just a large capacitor between the two GND islands what is a short circuit at the fundamental frequency. This is necessary to ensure good common GND connection for the C_even capacitors, since this example uses only one layer.
Design tip for dipole antennas
Question
How can I design a dipole antenna with good harmonic suppression?
Answer
Designing a printed dipole antenna directly to differential chip RF outputs makes always sense. This is mainly driven by cost considerations since the balun function can be eliminated from the RF front-end in this way. On the other hand, the ground plane (which size is critical in many cases) does not affect the performance of the differential-type antennas.
But, the filtering becomes more challenging on dipole antennas and a result of this high radiated harmonic levels might be observed. To fix this or to achieve better harmonic suppression the following filtering and matching method is suggested.
- Dipole antenna can be matched by its total length and a parallel capacitor (C_par) between its two ports
- The required parallel capacitance between the dipole ports (C_par) can be divided into two parts: C_odd and C_even
- One capacitor with C_odd value is suggested to be placed between the dipole ports
- Two capacitors with C_even values are suggested to be placed from each dipole ports to GND
- The C_odd capacitor can be tuned to become a good filter at one of the odd harmonics
- The C_even capacitors can be tuned to become good filters at one of the even harmonics
- Meanwhile, the total parallel capacitance (C_par) required between the dipole ports should be C_par = C_odd + [C_even*C_even / (C_even+C_even)] = C_odd + C_even/2. Since, the two C_even capacitors are in series connection with each other (through the common GND connection) and they are in parallel connection with C_odd.
Here is an example printed dipole antenna design for 2.4 GHz.
- 22nH is an RF choke inductor (shows high impedance at the fundamental)
- 3.3nH is a parallel inductor between the RF output pins to match the RF chip output
- 1.2pF is the C_odd capacitor
- 2x2.4pF are the C_even capacitors
- SMD1206 12pF is just a large capacitor between the two GND islands what is a short circuit at the fundamental frequency. This is necessary to ensure good common GND connection for the C_even capacitors, since this example uses only one layer.