Can the length of the Sync Word be defined as an arbitrary number of bits?
With Si443x chips or Si446x Rev B1 chips, the answer is: no, the length of the Sync Word must be defined in number of bytes (1 to 4 bytes in length).
With Si446x Rev C chips, the answer is: yes (almost). It is possible to configure Si446x_RevC chips for a Sync Word length that is an even number of bits, but it is not possible to configure the length to an odd number of bits.
This configuration is obtained by first "rounding up" the desired number of bits to next-highest byte count, and setting the SYNC_CONFIG:LENGTH API property to the appropriate enumeration. Example: if a Sync Word length of 14 bits is desired, this would be rounded up to 16 bits = 2 bytes, and the SYNC_CONFIG:LENGTH property field would be set to enumeration LENGTH = 1. The SYNC_CONFIG2:LENGTH_SUB property field would then be used to "subtract" an even number of bits from this defined length. Continuing this example of a desired length of 14 bits, it would be necessary to subtract 2 bits from the Sync Word length and thus the SYNC_CONFIG2:LENGTH_SUB property field would be set to enumeration LENGTH_SUB = 1.
However, it is always possible to "steal" an odd number of bits from the preceding Preamble field. For example, if a 13-bit Sync Word length is desired, the chip could be configured for a 2-byte = 16-bit Sync Word length. The desired 13-bit Sync Word value would be packed into the lower 13-bits of this 2-byte Sync Word definition, with the upper three bits defined as '010' or '101' (i.e., the tail end of the Preamble field just prior to the start of the Sync Word).
It is not possible to define a Sync Word length of zero bytes or bits. This has no meaning; it is not possible to find a bit pattern with a length of zero bits. However, it is possible to configure the chip to not care if a Sync Word is detected or not. This is accomplished by setting the PREAMBLE_CONFIG_STD_1KIP_SYNC_TIMEOUT bit.