Layout design practices around the output of an on-chip DC-DC converter
07/190/2015 | 03:15 PM
What are the layout design practices that should be considered when making the layout of a board that uses an on-chip DC-DC converter?
Make sure all the VDD pins of the chip are filtered individually with capacitors placed close to the related pins. If the VDD lines with poor filtering are close to the DC-DC converter output, interfering signals caused by voltage fluctuation of the DC-DC converter can get to these lines.
Jamming signal on the VDD is dangerous as it will spread out everywhere inside the chip.
Due to the far situated filter capacitors, the interference current travels on many long paths through the board, and gets back to the IC ground on a difficult way.
Long interference leakage paths on the PCB are dangerous in TX mode as these traces may behave as hidden antennas and cause unwanted emissions and violation of the radiation standards.
Many vias should be used around the output of the DC-DC converter. With missing vias to the ground, the ground plane does not work as a real unified ground anymore, and some parts work as a patch antenna and radiate, potentially causing again violation of the emission standards.
The leakage paths can cause the radio chip not to see a good ground reference (i.e. interference can be observed), and this may cause damage in RF performance (lower TX power, higher TX harmonics, higher current consumption, RX sensitivity loss).
If there is any GND pin close to the VDC pin on the chip, it should be connected to the GND pins of all the nearby filtering capacitors using many vias.
The layer beneath the layer where the chip with internal DC-DC converter is placed (basically the top layer) should be an equal ground layer, and should be disconnected by traces only if necessary.
For more detailed information (including a reference layout design), please refer to AN910 Application Note: