Do you have any recommendations for AFC configuration for AFSK decoding?
I have a working solution for 1200/2200 NRZI AFSK which suffers from a level of decoding failures in the DSP filtering + decoding running on the MCU.
Analyzing the data stream from the si446x shows asymmetrical PWM data which appears to be due to off frequency transmitters.
A significant amount of asymmetry is tolerated for stronger signals but this asymmetry combined with weaker signal strength produces sync (HDLC flag) acquisition failures or bad frame CRCs.
Any guidance on suitable AFC configurations would be appreciated.
You can increase the frequency offset measurement window to make it more accurate. This is detailed in chapter 4.2 in AN734. Note that the property that controls this parameters changed from revB1B to revC2A. Find the details here
I hope this is of help,
Thanks for the feedback.
Since asking the question I've experimented with both the LCM method driving RX_DATA and a configuration using just 1.2ksps (i.e just the symbol rate of the AFSK) feeding RAW_RX_DATA to my DSP chain (which has its own PLL locking to symbol rate).
I get better performance with the RAW_RX_DATA configuration thus far with off air signals (I'm yet to implement a more rigorous lab type test setup though).
The project has boards that have been manufactured with 4464 (B1B) but also some have 4463 (C2A).
I do see differences in performance between the 4463 and 4464 (better performer of the two).
I'm running the 4463 in 4464 compatibility WRT the setting of MODEM_RAW_SEARCH2 (set to 0).
Note I do apply the patch to the 4463 (C2A).
So the 4464 and 4463 should perform similarly as far as I can discern.
One question I had was on the settings of the decimator CIC in the 4464.
In the 4463 there is MODEM_DECIMATION_CFG2 which can control gain and AGC options of NDEC2.
Q: The 4464 has no control of these parameters and I wonder what the behind the scenes behavior of CIC stage 2 is in the 4464 and thus what should the 4463 be set to in order to behave the same as the 4464?
I also wanted to try gear switching with different IF filter widths (gear switch on AFC min-max eye threshold).
Unfortunately when using WDS and specifying different RX bandwidth WDS chooses different decimation settings between two bandwidths.
Thus the filter coefficients from wider [12.5KHz] (pre- gear switch) WDS setup can not be used with another narrower [8.4KHz] (post gear switch) set of coefficients since WDS selected a different decimation setup/sample rate.
Q: I guess I could recompute the narrow FIR coefficients based on the wider coefficients using the known sample rate etc. but thought you may have another suggestion or an option for WDS to have it generate the two differing bandwidth configuration coefficients using the same sample rate?
FYI The project using the 446x is now getting more complicated as we add new PHY to it for other modulation/speed and also additional bands (new board has 2 x 446x).
I may have some more questions soon....
It was not clear which variant behaved the better in your tests. Can you clarify pls?
Q1: Si4463 revC2A has an extra decimator stage to be used for very narrowband (< 1 kHz) Rx applications. In your case this should be bypassed to emulate the Si4464 configuration.
Q2: WDS can do the calculation for you. If on a packet mode project you select below two features on the RF parameters tab.
Note that he bottom one only becomes visible once you have enabled the top one. This feature will select a 2nd set of filter coefficients for signal tracking. Both the acquisition (wider) and tracking (narrower) filter are using the same decimator chain configuration. You can change the wider bandwdith as you like by changing the XO accuracy on the Frequency and Power tab.
This is how you can verify the calculated filter configuration:
Apologies for slow reply. I didn't have follow set on this post so didn't get a notification. Fixed now.
Part I of my reply...
Anyway regarding which configuration was the better performer...
A: The configuration which performed the best was using the 4464 (B1B) with output of RAW_RX_DATA which is then processed by a DSP chain in the MCU (STM32). Using RX_DATA and LCM (26.4ksps) method did not perform as well. Also 4463 (C2A) running as 4464 compatible does not perform as well as 4464.
The data rate in WDS I set for the RAW_RX operation is a simple 1.2ksps.
Subsequent to those tests there have been many changes to the front end PWM handler, HDLC handler and DSP filter/decode processing code.
The decode success rate has been improved substantially in general and also under conditions of heavy RX traffic .
e.g. During high altitude balloon flights (one use case for this project) the AFSK traffic is often continuous/overlapping.
Anyway I will try the LCM (26.4ksps) method driving RX_DATA again shortly and see if there remains a verifiable difference between the 1.2ksps outputting RAW_RX and the 26.4ksps output BCR managed RX_DATA.
The majority of the 446x driver code is now able to support changes of band and PHY, etc. for AFSK RX/TX and 2FSK TX. At some point I'll be working on 2FSK RX (with non-standard preamble and whitening polynomial not supported by 446x) so that will take some fiddling with pre-amble detection and non-standard PH processing.
Continued in next post...
Part II of my reply...
Regarding the NDCE2 decimator stage...
Thanks for the clarification. I did have NDCE2 set as disabled for the 4463 (C2A) boards running in 4464 compatibility mode.
Good to know that was already correct.
Regarding filters and gear switching...
Thank you for the information on how to get the result required from WDS.
I have to figure out a scheme to reset/restart the gear switch in AFSK mode (perhaps mission impossible due to the PWM front end and the decoder back end operating primarily asynchronously).
However, It should be possible for 2FSK so I will definitely produce some coefficients and give gear switching a try for 2FSK RX when I get to that stage.
A question on RSSI dBm calculation...
I found a formula in the API docs and an EZR Reference Manual(s) for expressing RSSI in dBM.
This was dBm = ((RSSI / 2) - Si446x_MODEM_RSSI_COMP_VALUE - 70).
Another formula in the EZR document gives RSSIdBm = (RSSI_value/2) - 130 which fails to consider the MODEM_RSSI_COMP.
For this next formula with the default for MODEM_RSSI_COMP of 64 the offset value is 70 + 64 = 134 which is different to the 130 in the first formula.
Anyway could you confirm the above first formula I have used is correct or advise a correction if it is wrong?
I have code that calculates and sets the IF_FREQ as required using the formulas in the API docs.
However, there is no formula for calculating FREQ_CONTROL_VCOCNT_RX_ADJ in the API docs.
I deduced this calculation to be = -((FREQ_IF * OUTDIV) / (PRESCALER * WSIZE)) / XO and am currently using that.
Is my deduced formula correct?
Can you provide a formula for calculating the AFC limiter?
Thanks and best regards