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      • Automatic actions based on RSSI measurements on Si446x

        zopapp | 08/220/2014 | 10:00 AM

        Automatic actions based on RSSI measurements on Si446x

         

        1.       RSSI Interrupt

         

        The RSSI interrupt gets activated if the current RSSI level is above (crosses) the RSSI threshold defined in API property MODEM_RSSI_THRESH. Regardless of how the MODEM_RSSI_CONTROL or MODEM_RSSI_THRESH or FRR_CTRL_X_MODE properties are configured, the source for the RSSI interrupt in Si446x chips is always the comparison of the Current RSSI value with the programmed MODEM_RSSI_THRESH value.  That is to say, the RSSI interrupt (bit D3 of the MODEM_STATUS response byte returned by the GET_INT_STATUS command) is always generated by comparing the Current RSSI value with RSSI_THRESH, and never by comparing the Latched RSSI value with RSSI_THRESH. The interrupt remains active until it is either cleared or the receiver is restarted by either its automatic state machine or by the host MCU.

         

        1.       Latched RSSI check

         

        There is potential for confusing the RSSI interrupt with another function involving the Latched RSSI value.  In the MODEM_RSSI_CONTROL property, there is a function called CHECK_THRESH_AT_LATCH (bit D5).  If this bit is set, then indeed the Latched RSSI is compared with the RSSI_THRESH value.  However, the purpose is to determine if the Latched RSSI value does not exceed the threshold.  If the Latched RSSI exceeds the threshold, no interrupt occurs and the reception of the packet continues normally.  If the Latched RSSI is below the threshold, then the chip transitions to the START_RX:RXTIMEOUT_STATE and generates an INVALID_PREAMBLE interrupt (if enabled). When frequency hopping is utilized one of the conditions upon which the receiver tunes to the next frequency is INVALID_PREAMBLE. The feature described in this paragraph generates an INVALID_PREAMBLE if the Latched RSSI value stays below a threshold defined by MODEM_RSSI_THRESH. So in other words if no signal power is detected in the channel the receiver can be made to go to the next frequency.

         

        1.       CCA signal

         

        The CCA (Clear Channel Assessment) signal is one of the signals that can be output to one of the GPIOs (look for GPIO_PIN_CFG in the API document). It goes high if the current RSSI value is above the threshold given in MODEM_RSSI_THRESH and goes low if the current RSSI value is below this threshold. This signal is continuously updating as long as the receiver is on.

         

        1.       CCA latch signal

         

        The CCA latch (Clear Channel Assessment latch) signal is one of the signals that can be output to one of the GPIOs (look for GPIO_PIN_CFG in the API document). There is the potential for confusing the Latched CCA signal, with the Latched RSSI signal.  The Latched CCA signal is *not* developed by comparing the Latched RSSI signal with the RSSI Threshold.  Instead, the Latched CCA signal is developed by “remembering” the CCA signal (developed from the Current RSSI comparison with the RSSI Threshold) by a latching function. The CCA latch signal remains asserted until either sync word is detected or the receiver is restarted.

         

         

         

        1.       Squelching function

         

        Squelching of the RX_DATA output may be configured conditional (amongst other measures) on the current RSSI reading. If current RSSI remains below the RSSI threshold defined in API property MODEM_RSSI_THRESH there will be no toggling on RX_DATA whereas if it is above this level there will be toggling on RX data. See filed SQUELCH in API property MODEM_OOK_CNT1 for more details.

      • RSSI accuarcy on SI4x6x

        zopapp | 08/220/2014 | 09:18 AM

        Question

        How accurate is my RSSI reading on Si4x6x rev B1B?

        Answer

        The question in the title can be interpreted in two ways:

         

        1.        How accurate is my RSSI reading on any one chip? 
        2.        How much variation can I expect from chip to chip?

        We will cover both of these topics in this article. Before we dove into measurement results however, here is a brief overview of RSSI operation on the chip.

         

        There are two different RSSI values that can be read back from the chip. One is latched RSSI the other one is current RSSI. Current RSSI reflects the measurement value at the latest 1Tb time period and gets updated in each 1Tb time period. As indicated by its name latched RSSI is only one RSSI value that is captured from the current RSSI value at a specific point in time in the receive process. The receiver will retain this latched RSSI value until it is re-started by either the automatic state machine on the chip or by the host MCU. The latching event can be configured in filed “LATCH” in API property “MODEM_RSSI_CONTROL”.  Find below a recap of what possible events can be set for latching.

         

        Name

        Value

        Description

        DISABLED

        0

        Latch is disabled. The returned value of the Latched RSSI will always read 0.

        PREAMBLE

        1

        Latches RSSI at Preamble detect.

        SYNC

        2

        Latches RSSI at Sync Word detect.

        RX_STATE1

        3

        Latches RSSI at 4*Tb after RX is enabled (7*Tb if AVERAGE = 0).

        RX_STATE2

        4

        (only with AVERAGE=0) Latches RSSI at 8*Tb after RX is enabled.

        RX_STATE3

        5

        (only with AVERAGE=0) Latches RSSI at 12*Tb after RX is enabled.

        RX_STATE4

        6

        (only with AVERAGE=0) Latches RSSI at 16*Tb after RX is enabled.

        RX_STATE5

        7

        (only with AVERAGE=0) Latches RSSI at 20*Tb after RX is enabled.

         

        Note, that options “PREAMBLE” and “SYNC” only make sense in packet mode operation. Don’t use them in direct mode applications! A few of the entries in the table refer to a value called “AVERAGE”. The current RSSI value (that is to become the latched RSSI value at the latching event) gets updated at 1*Tb bit period intervals, however this value can either be the result of one measurement on the previous 1*Tb cycle or the average of the previous 4*Tb bit cycles. The “AVERAGE” value decides between the two modes of operation in the following fashion:

         

        Name

        Value

        Description

        AVERAGE4

        0

        The RSSI value is updated at 1*Tb bit period intervals but always reflects the average value over the previous 4*Tb bit periods.

        BIT1

        2

        The RSSI value is updated every 1*Tb bit period.

         

        Averaging over 4 bit periods will make the reading more accurate at the price of delaying the 1st valid reading by 3Tb. So the setting of this field must be a result of a trade-off between accuracy and 1st valid RSSI access time.  This averaging setting is applicable to both the current and latched RSSI values.

         

        Both the latched and current RSSI values can be read back with the GET_MODEM_STATUS command (refer to the API document for details). On top of this the latched RSSI value can also be read back from one of the FRRs (Fast Response Register) to shorten the access time. Refer to section FRR_CTL in the API document for details. To avoid confusions it is important to note that the current RSSI value cannot be read back from the FRRs. Now, let’s get back on the original questions. 

         

        1.      How accurate is my RSSI reading on any one chip? 

        This question translates to quantifying somehow the spread one may see on the results when reading back the current RSSI value at the same input power level.  If we assume a normal distribution on the RSSI samples the standard deviation of the results will give us insight into the repeatability of the reading at any one power level. Below graph shows both the average and the standard deviation of the current RSSI value read back 500 times at each power level parameterized with different DR settings – 1, 40, 100 and 500 with Rx bandwidths of 2kHz, 93kHz, 206kHz and  825 kHz, respectively . No averaging was configured on the chip itself.

         

         RSSI_curves_all_DR.PNG

         

        Both ends of the curves are clipped to some fixed value. At the higher end of the dynamic range this value is constant over DR settings. At the lower end of the dynamic range however this value changes with DR. The lower the DR the narrower the filter bandwidth which in turn means less noise the receiver is seeing hence the lower clipping value (also referred to as noise floor).  Also interesting to note that at the lower end of the dynamic range the standard deviation of the reading is higher. Fundamentally on noise the standard deviation is higher and as long as the wanted signal remains close to the noise floor the reading also remains noisy.  

         

        Now what to make of all of this data?  Let’s take one example. Let’s examine the question of how many times do I need to read back the current RSSI value at sensitivity level to be able to say that my averaged result always stays within +/- 1 dB.

         

        Typically sensitivity level is 10 dB above the noise floor (this is true for 2GFSK cases with modulation index of 1). Let’s zoom onto one of the traces (40 kbps) from the above plot for this example.

         

        RSSI_curves_40_kbps.PNG

         

        Our noise floor is around 26 RSSI codes. As 1 RSSI code means 0.5 dB jump in power level our expected sensitivity level is around 26 + 2*10 = 46 RSSI codes (from the graph this means around -111 dBm). Our standard deviation value at this point is around 4.5 RSSI codes. If we assume a normal distribution the probabilities of a read back staying within so many standard deviations from the average are the following:

         

        distance from average in standard deviation

        probability of read back staying within the distance

        1

        0.682689492137

        2

        0.954499736104

        3

        0.997300203937

        4

        0.999936657516

        5

        0.999999426697

        6

        0.999999998027

         

        Let’s pick a 1ppm failure rate that corresponds to a distance of 5 standard deviations. (This means that only 1 read back will be outside of the +/- 5 standard deviation window in a million reading.)  So returning to our example the read backs at sensitivity level will be staying within +/- 22.5 codes of the average value at a failure rate of 1 ppm. This translates to +/- 11.25 dB.  This value does not meet our original +/- 1dB specification, our standard deviation is too high for that. We would need a standard deviation of 0.4 RSSI code to stay within the +/- 2 RSSI code target.  With averaging the standard deviation scales with the square root of the averaging number. (st_dev_avg_N = st_dev / sqrt(N) ).  We need to scale down the standard deviation by a factor of 4.5/0.4 = 11.25, which means an averaging of 11.25^2 = 126.5625 which rounded up yields a number of 127.  So if a +/- 0.5 dB accurate RSSI reading is needed at sensitivity level current RSSI must be read back 127 times (at least 1Tb apart) and an average must be calculated.

         

        This has been an extreme example but following the logic you can calculate your RSSI reading accuracy to a certain confidence level around sensitivity using the data from the 1st graph.

         

        As a more realistic example if averaging over 4Tb is used on the chip the standard deviation numbers on the graphs will get halved meaning around 2.25 RSSI codes at sensitivity level.

         

        There is one more important aspect that is worth mentioning in this section. As you can see from the graphs the standard deviation does not converge to 0 with ever higher input power levels. One would expect this behavior as the SNR (Signal to Noise Ratio) increases. At this region (from sensitivity + 20 dB to the upper clipping end of the dynamic range) the deviation we are seeing is not caused by noise but rather the mode of implementation of the RSSI measurement. This means a 1 dB ripple on read back value. What is important here is that read back distribution is no longer normal so the calculations above do not hold in this region. The RSSI read back simple toggles between (at most) 3 codes.

         

        1.      How much variation can I expect from chip to chip?

        In this section we examine how much the average reading changes from chip to chip at a given power level. We assume that the RSSI curves look the same on each chip and only focus on how much these curves can shift. For this find below a CCDF (Cumulative Complementary Distribution Function) that shows the distribution of the average RSSI reading at a decent -60 dBm input power level on 20 chips taken from various lots parameterized also with temperature.

         

        CCDF_RSSI_avg.PNG

         

        Temperature [degreeC]

        -40

        25

        85

        Average [RSSI code]

        152,651

        150,445

        146,6925

        Standard Deviation [RSSI code]

        0,983281

        0,999483

        1,168422

         

        Assuming normal distributions again one can calculate the RSSI shift from part to part to a certain confidence level following the logic from the previous chapter.  As an example at room temperature the parts will read back an average RSSI value that stays within +/- 2.5 dB of the average of the whole population.

         

        This variation however can be eliminated with a one point calibration at production test. API property MODEM_RSSI_COMP contains an offset value that directly affects the RSSI reading.

         

        modem_rssi_comp.PNG

         

        A larger compensation value will adjust the returned RSSI value upwards, and a lower value will adjust the RSSI value downwards.  Refer to the API document for more details. Note, that the resolution of the RSSI reading restricts the accuracy of the calibration to +/- 0.5 dB.

         

        As you can see from the graph there is a consistent shift on the curves with temperature. This is around a 2 RSSI code increase from 25 to -40 degree C and a 4 RSSI code decrease from 25 to 85 degree C. This shift however may be compensated by utilizing the on-chip temperature sensor.

      • RF layout routing suggestions

        zovida | 08/219/2014 | 10:37 AM

        Question

        What are the most important rules/suggestions when designing the RF layout section?

        Answer

        - If the design uses more than 2 layers it is always recommended to put the VDD line and as many digital traces as possible in an inner layer and use as large and continuous solid ground planes for the top and bottom layers as possible. In this way the top and bottom layers can act like natural shields and the risk of the unwanted harmonic and spur radiation issues can be minimized.

        - It is also important to keep the ground plane area under the RF chip and matching network unbroken on the first inner layer.

        - Minimize the distance between the neighboring matching components. Move the matching network (especially the TX path) as close to the RFIC as possible.

        - Nearby inductors should be perpendicular to each other in order to avoid the couplings between them.

        - Place the crystal or TCXO as close to the RFIC as possible.

        - Have at least 0.5mm separation between the traces/pads and GND top metal in the RF matching network.

        - Place the RF output, antenna far away from any digital lines connected to the RFIC in order to avoid the possibility of latch-up issues (especially in high output power cases).

        - Have an option for shielding can above the matching/RFIC/XTAL area.

         

        - Always try to follow as much as possible our reference designs' RF layout routing.

        - Other suggested collateral: AN629/685/791. 

         

         

         

         

      • Harmonic radiation issue with Si4x6x RF chips

        zovida | 08/219/2014 | 06:51 AM

        Question

        I see high radiated harmonics with Si4x6x radio chips with even good conducted results. What can be the main source of the harmonic radiation?

        Answer

        If the conducted spectrum looks good in terms of output power at the fundamental and at the harmonics too the harmonic content of radiation is likely not radiated via the antenna. In that case the VDD lines can be suspicious, since the harmonic content (generated in the switched mode PA) can go through the choke inductor (through its parasitic capacitance at the higher frequencies) and can be radiated out by the VDD traces. In that case the harmonic filtering of those VDD traces becomes more important and suggested.

         

        Moreover, traces connected to the SDN, GPIO 2 and 3 pins might be the main radiators of the unwanted harmonics, so the additional filtering of those traces is also recommended. 

      • Harmonic radiation issue with Si4x3x and Si10xx RF chips

        zovida | 08/219/2014 | 06:46 AM

        Question

        I see high radiated harmonics with Si4x3x and Si10xx radio chips with even good conducted spectrum. What can be the main source of the harmonic radiation?

        Answer

        If the conducted spectrum looks good in terms of output power at the fundamental and at the harmonics too the harmonic content of radiation is likely not radiated via the antenna. In that case the VDD lines can be suspicious, since the harmonic content (generated in the switched mode PA) can easily go through the choke inductor (through its parasitic capacitance at the higher frequencies) and can be radiated out by the VDD traces. In that case the harmonic filtering of those VDD traces becomes more important and suggested. 

      • Matching network design

        zovida | 08/219/2014 | 06:16 AM

        Question

        What are the main design differences between the different matching network types?

        Answer

        1) RX

         

        This is a conventional complex conjugate matching. The required differential balun matching impedance should be the complex conjugate of the differential RX input impedance of the chip. The single ended side impedance of the matching balun network is 50 ohm.

        Details in AN643 app note.

         

        2) TX

         

        a) Class-E (CLE)

        Not a conventional matching procedure. The transistor should be only considered as a switch (switched mode PA). Here, the goal is to get matched for the desired output waveform (Class-E type voltage and current waveform). For this the required load impedance can be calculated what depends on the internal parallel shunt capacitance and frequency. The output power depends on the frequency, shunt capacitance and supply voltage. The shunt capacitance is given, included inside the chip and has different values for the Si4460/61/63/64 RFICs from 1.25 to 2.5pF. At a given frequency the maximum achievable output power is larger if the shunt capacitance and/or supply voltage are also larger. With a given shunt capacitance the maximum achievable output power is larger if the frequency and/or supply voltage are also larger. At a given frequency the different RFIC types (Si4460/1/3-4, i.e. different shunt capacitance) need different matching network values. Advantage is the very good power efficiency (i.e. low current consumption). Disadvantages are the quite strong VDD dependency in the output power level and the relatively higher voltage swing at the output TX pin.  

         

        b) Square-Wave (SQW) 

        Not a conventional matching procedure. The transistor should be only considered as a switch (switched mode PA). Here, the goal is to get matched for the desired - square wave - output waveform. For this it is required to load the chip TX output with a fixed impedance in wide-band. We have to ensure the same impedance for the fundamental and even for the harmonics to get the square wave output waveform. The harmonic trap parallel resonant circuit with loaded Z ohm impedance ensures the required termination for the harmonics, meanwhile shows high impedance for the fundamental what is driven forward via the filtering section what shows the required Z impedance. So, in this way the harmonics are filtered and terminated by Z ohm and the fundamental is also terminated with Z ohm by the filter. Z is typically 50 ohm. The matching values only depend on the frequency. It has good efficiency, lower voltage swing and more acceptable VDD dependency compared to Class-E.

         

        c) Switched-current (SWC)

        This is a more conventional PA matching procedure. The TX output stage can be imagined as a current generator what pumps fixed current to the load. The output power based on the amount of the current can be handled by setting the load impedance. At a given current the output power is higher if the load impedance is higher. The limitation here is the maximum allowed voltage swing at the output TX pin tolerated by the chip. At a fixed output power level the best efficiency (i.e. lowest current consumption) can be achieved with the largest load impedance while the voltage swing has an acceptable value at the TX output (do not cause degradation). Reducing the load impedance value the efficiency becomes worse, but the matching will become more robust against the VDD dependency. 

         

        TX matching procedure details can be found in our AN627/648 app notes.