Proprietary Knowledge Base

      • Design tip for dipole antennas

        zovida | 10/293/2014 | 11:35 AM


        How can I design a dipole antenna with good harmonic suppression?


        Designing a printed dipole antenna directly to differential chip RF outputs makes always sense. This is mainly driven by cost considerations since the balun function can be eliminated from the RF front-end in this way. On the other hand, the ground plane (which size is critical in many cases) does not affect the performance of the differential-type antennas. 


        But, the filtering becomes more challenging on dipole antennas and a result of this high radiated harmonic levels might be observed. To fix this or to achieve better harmonic suppression the following filtering and matching method is suggested. 

        - Dipole antenna can be matched by its total length and a parallel capacitor (C_par) between its two ports

        - The required parallel capacitance between the dipole ports (C_par) can be divided into two parts: C_odd and C_even

        - One capacitor with C_odd value is suggested to be placed between the dipole ports

        - Two capacitors with C_even values are suggested to be placed from each dipole ports to GND

        - The C_odd capacitor can be tuned to become a good filter at one of the odd harmonics

        - The C_even capacitors can be tuned to become good filters at one of the even harmonics

        - Meanwhile, the total parallel capacitance (C_par) required between the dipole ports should be C_par = C_odd + [C_even*C_even / (C_even+C_even)] = C_odd + C_even/2. Since, the two C_even capacitors are in series connection with each other (through the common GND connection) and they are in parallel connection with C_odd.


        Here is an example printed dipole antenna design for 2.4 GHz.



        - 22nH is an RF choke inductor (shows high impedance at the fundamental)

        - 3.3nH is a parallel inductor between the RF output pins to match the RF chip output

        - 1.2pF is the C_odd capacitor

        - 2x2.4pF are the C_even capacitors

        - SMD1206 12pF is just a large capacitor between the two GND islands what is a short circuit at the fundamental frequency. This is necessary to ensure good common GND connection for the C_even capacitors, since this example uses only one layer.


      • Si4356 VDD requirement

        zovida | 10/290/2014 | 10:50 AM


        What is the VDD requirement of the Si4356 radio chip?


        Supply voltage range: 1.8 - 3.6 V


        The Power-On-Reset sequence should be also followed for the proper operation as in case of Si4355.


        "A Power-On-Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this process, VDD must ramp within 1ms and must remain applied to the device for at least 10ms. If VDD is removed, then it must stay below 150mV for at least 10ms before being applied again."


      • High radiated harmonics on loop antenna with Si4010/11/12

        zovida | 10/289/2014 | 10:33 AM


        I see high radiated harmonics with a Si4010 keyfob using loop antenna. How can I reduce the unwanted harmonics?


        To get better suppression on the radiated harmonics the followings are suggested to be tried.


        • Reduce the top antenna capacitor value. This capacitor is responsible for the proper impedance transformation. If its value is higher the chip termination impedance is also higher what can cause higher harmonic contents. The typical top antenna capacitance is between 1.5 and 2pF for a 25x25mm loop antenna at 434MHz. With a same-sized loop it is lower than 0.5pF at 868MHz. Larger loops require lower capacitor values.  
        • Make sure of the antenna symmetry.
        • Use copper pour on both top and bottom layers connected to each other with many vias, where there is at least 2-3mm keep-out between the copper pours and antenna traces. 
        • Filter the VDD trace with parallel capacitors at the critical frequency. 
        • Switch off the PA Max Drive.
        • Reduce the PA Power Level.



      • Si446x pin 18 (GNDX) connection

        zovida | 10/289/2014 | 10:14 AM


        What is the correct connection of pin 18 of the Si446x RF chips? GND or NC?


        The recommended connection depends on the used crystal oscillator type.


        - When using an XTAL, leave floating per our reference design schematic. 

        - When using a TCXO, connect to the TCXO’s GND what should be separated from the board’s reference ground plane per our reference design. 


      • Si446x pin 5 connection

        zovida | 10/289/2014 | 10:06 AM


        What is the correct connection of pin 5 of the Si446x RF chips? GND or NC?


        It is recommended to connect this pin to GND per our reference design schematic. Not connected internally to any circuitry.


        The reason for connecting this pin to GND is to achieve good RF grounding effect through that pin. In this way a good RF ground reference can be ensured for the VDD filtering capacitors by connecting the chip exposed pad's ground to the filtering capacitors' ground pads.


      • How to Setup Multi-Networking With the Framework.

        dprodrig | 10/283/2014 | 12:05 PM


        How to Setup Multi-Networking With the Framework.


        This knowledge based article will help you get your application setup with multi-network capability. If you are interested in details about what multi-networking is, please read up on the document documentation/ApplicationNotes/AN724_Multinetwork.


        For instance, here is an excerpt from the document:

        "A multi-network device may operate on either two different SE networks or on an HA network and an SE network. Beginning with EmberZNet 5.3, a multi-network device may also operate on two different HA networks. In a multi-network configuration, the device must join at least one network as a sleepy end device. It may act as a coordinator, router, end device, or sleepy end device on the other network. HA and SE are the only supported security types. ZLL devices are not supported."


        Another stipulations about multi-networking to be aware of is that multi-networking is stripped out of EM2xx and EM351 platforms in order to save flash.


        1. The first thing you need to do is add a second network in the General Tab >> Network Configuration field.
        2. Once you do that, App Builder will allow you to go into ZCL Clusters Tab >> Multiple endpoint configuration field to create a new endpoint that uses a different network.
        3. After creating a second endpoint, in the endpoint field go to the "Network" and select the second network.
        4. Finally, in the Znet Stack Tab >> Network Configuration field you can setup your second network device type and security.

        One of the advantages of using our framework when using multi-networking is that all of the plugins have been modified to natively support multi-networking.


        When starting with multi-networking, it may be benificial to investigate the emberAfPushXXXNetworkIndex functions described in app/framework/include/af.h as well as functions containing “NetworkIndex” in the name. These functions are useful APIs when dealing with multi-network operations.

      • PCIe 时钟发生器和时钟缓冲器的最大偏差率

        Nari | 10/281/2014 | 08:26 AM



        诸如 HCSL 的电流模式缓冲器理论上拥有一个驱动电容负载 C L 的电源 I OUT 。 因此,偏差率按如下公式设置:

        SR MAX = I OUT /C L

        如果应用程序需要更大的偏差率, I OUT 值必须 增大。 如何估计既定 SR MAX 规格所需的 I OUT ?

        1 . 数据表中并非始终提供 I OUT 。

        2 . 但是,单端信号摆动 V SWING 已给出。

           a . V SWING = I OUT *R T ERM ,其中 R TERM 是 Diff 、 Diff# 和地面之间的有效终端电阻,对于 HCSL 来说,其值为 50 ohm 。

        3 . 因此,如果要求满足 SR MAX 规格,那么就应该对 V SWING 进行设置。 I OUT 和 SR MAX 也应该进行相应设置。 对于 Silicon labs PCIe 时钟发生器和缓冲器系列,必须通过 i2c 接口编程以下寄存器才可以设置摆动。



        寄存器地址为 5 ,此选项仅对以下 Si Labs PCIe 产品可用: Si52142 、 Si52143 、 Si52144 、 Si52146 、 Si52147 、 Si53152 、 Si53154 、 Si53156 、 Si53159 。