Using a 2-layer PCB in the application hardware is usually preferred by customers due to cost saving purposes. Still, based on the RF output power level, unwanted radiation of top or bottom layer traces (mostly VDD or digital) can occur, which causes that the application can violate the harmonic limits of the related standards. In order to minimize the possibility of unwanted trace radiations, Silicon Labs recommends to use multilayer PCBs in the following cases:
>=10dBm output power at 2.4GHz
Note that the actual recommendation depends on which standard (ETSI, FCC, ARIB, etc.) the application has to be compliant with.
One can notice that not all Silicon Labs reference design follows the above listed recommendations. EZRadioPRO reference design boards are made on 2 or 4 PCB layers based on the output power, while all EZR32 and EFR32 reference design boards are using 4 or 6 PCB layers due to the complexity of the design. In the latter case, the layout routing could not be realised on a 2-layer PCB if all digital traces were intended to be used. Of course, on a custom design where the complexity of the design is much less, 2-layer PCBs can be used for EZR32 or EFR32 applications as well considering the above listed recommendations.
Silicon Labs provides RF range calculators for customers to help estimating the actual range of their wireless applications. Simple RF Range Calculator is available to download from the following link below.
RF range depends on the following parameters:
Simple RF Range Calculator
Simple RF Range Calculator is for those customers who don’t want to deal with difficult RF questions, just simply would like to get fast and reasonable results for both outdoor and indoor environments.
Simple RF Range Calculator provides fast and accurate result as the customer selected the frequency band and set TX and RX parameters.
Frequency bands and custom frequency channels can also be selected.
TX Output Power and RX Sensitivity need to set up based on the radio device’s actual link parameters based on the data sheet.
If the exact antenna parameters are unknown notes at the right side can help to determine the closest values.
The achievable RF range depends on many other factors as well. See the following KBA article for further details on RF range factors:
How can I make the frequency bandwidth of PCB antennas wider?
In some cases/applications the BW of printed antennas might not be sufficient. This article summarizes some design tricks on how to make a printed antenna wider bandwidth.
- Increase the board size (e.g. GND plane in the case of monopole-type antennas). Avoid using RF modules that have smaller size than quater-wavelength. Small modules generally have poor antenna gain and narrow bandwidth (due to the high Q factor).
- Increase the board thickness. Of course, it's typically limited by design.
- Decrease the dielectric constant of the PCB. Select PCB material with low epsilon value.
- Use wider and/or tapered traces in the PCB antenna structure.
- Use coupled traces in the PCB antenna structure. Coupled structures typically have wider frequency bandwidth.
- Do some tricks in the external antenna matching network. I.e. use more components to do the match (to stay within a given constant Q ellipse on the Smith Chart); create resonators in the matching network. Also, see Bode-Fano, Youla matching techniques.
A number of antenna types can inherently be matched to the desired input impedance (typically, 50-ohm single-ended) without using any external tuning component (e.g. printed inverted-F antenna). However, board size, plastic enclosures, metal shielding, and components in close proximity to the antenna can affect antenna performance. For best performance, the antenna might require tuning that can be realized by two ways:
It is typically a preferred solution when layout modification is not required on a custom design. To accomplish this, Silicon Labs generally recommends to ensure SMD placeholders for external antenna tuning components, where the suggested external antenna matching structure is a 3-element PI network. You can achieve a good match using as a maximum of two elements (with one series and one shunt component) of the PI network. Any unknown passive impedance can get matched to 50 ohms on this PI network, since all L, C, L-C, C-L combinations can be realized on it and therefore any de-tuning effect can be compensated out.
Note that every implementation of an antenna design might require different combinations of inductors and capacitors.
Recommended 3-element PI network for external antenna matching purposes:
What kind of RF-switch is recommended for the replacement of the uPG2164 DPDT RF-switch used in most of the Si4x6x-based reference designs?
The RF-switches listed below can be good alternatives to replace the uPG2164 DPDT RF-switch. These switches have approximately the same specifications/characteristics/ratings and footprint as the uPG2164.
Example list of RF switches for the replacement:
The RF switch used in the designs needs to have:
- low insertion loss
- high enough frequency capability
- high isolation
- high enough power capability
- low harmonic re-generation, i.e. low distortion
- small size
How should I route the traces on more-layer RF designs for optimal performance?
In order to achieve the possible best RF radiated performance the followings are suggested for more-layer RF board designs:
- Top Layer: Components and short traces. Top layer should use as large and continuous GND plane metallization as possible (with many stitching GND vias) on the entire PCB.
- 1st inner layer: GND plane and traces if necessary. The most important rule is to keep the GND pour metallization unbroken beneath the RF areas (between the antenna, matching network and RF chip). Traces can be routed under the non-RF areas and use GND pour where possible.
- 2nd, 3rd... inner layers: Traces. VDD and all other traces are suggested to be routed on these layers. Use GND pour where possible.
- Bottom Layer: GND plane. Use as large and continuous GND plane as possible. Do not route traces on this layer, just if it is necessary, e.g. short connection traces to connectors.
- Generic for each layer: Try to avoid routing traces along or close to the board edges. It is recommended to place ground stitching vias with GND pour along the PCB edges.
What are the general layout suggestions for RF board design?
Here are some layout hints that are suggested to follow for nay kind of RF board designs.
- use as large and continuous GND metallization as possible on all layers
- use plenty of GND stitching vias on the enrite PCB, especially at the board and GND metal pouring edges.
- do not route traces at the board edges
- place the high frequency crystal close to the RF chip
- connect the crystal case to GND
- use short VDD traces
- if possible, shield the VDD traces by ground metallization (with vias) from both sides
- put the matching network as close to the RF chip as possible to minimize the parasitics in the RF-FE match and avoid de-tuning
- make sure that there are many GND vias on the RF chip's exposed pad
- further recommendations are in the layout-related application notes.
More layout suggestions can be found in application notes: AN629, AN928, for instance.
On the EZRadioPro and EZRadio devices the Rx (Receive) state machine can automatically change the device’s state upon three different events:
Let’s have a look at these events and the mechanisms that can make them occur!
RX TIMEOUT: Generally speaking this is an event that signals that there has been no signal detection in the current receive process (i.e., from the time instant the receiver got started / re-started). There are a few mechanism that can provide this signal.
RX VALID: This event simply signals that a packet has been received without a CRC error. Note that if no CRC check is configured in the packet handler, all received packets (albeit erroneous) will be also deemed valid packets.
RX INVALID: This event simply signals that a packet has been received with a CRC error. Note that if no CRC error check is configured in the packet handler, this event will never come about.
Now, in the START_RX command a state can be defined for all above described events (look for arguments RXTIMEOUT_STATE, RXVALID_STATE, RXINVALID_STATE at the START_RX API command) where the automatic state machine will bring the part upon the occurrences of these events.
Let’s go through the typical state transition use cases:
0: NO CHANGE: There will not be any change in the receiver’s state whatsoever. This is the recommended value for the RX TIMEOUT event in normal (i.e., not LDC or PSM) continuous receive mode. One might say the 8: RX_STATE is as good a state transition as no change in such a case. When RX_STATE is selected however, the receiver does get re-started making it blind for a few 100 us while the calibrations are completed. Note also that in automatic frequency hopping Rx application at NO CHANGE the receiver will still hop onto the next channel.
1: SLEEP: This is the recommended value for the RX_TIMEOUT state when in automatic LDC RX mode. The part will be sent back to SLEEP state if no signal is detected in the channel.
3: READY: This state is recommended after a (valid) packet has been received. There are a few advantages of using READY state as opposed to restarting the receiver straight away. (1) The latched RSSI and frequency error measurement values are reset upon entering into RX state therefore if the host FW is not quick enough at reading them they may get lost if automatic RX STATE transition is selected. (2) If the receiver is sent back to RX STATE automatically another packet may be being received while the previous one is being retrieved from the FIFO calling for very careful FIFO handling from the host not to lose parts of packets.
8: RX: This state transition can be used after a (valid/invalid) packet has been received taken above considerations (at READY state) into account.
9: IDLE: This state transition is used by the Preamble Sense Mode (PSM) operation where the receiver is duty cycling in a short term basis. The part will transition into this state of no signal has been detected by the DSA block.
Independently of all above described there is another automatic state machine running in the demodulator while the part is Rx state. (Let’s call this state machine the demodulator state machine and one discussed above the Rx state machine.) It has got three states: (1) Preamble search, (2) Sync word search (3) Packet Receive. Note that the demodulator state machine always gets reset when the Rx state machine transitions into Rx state.
Let’s have a look at the two commonly used packet based receive processes!
All the considerations on the demodulator state machine hold for both the EZRadioPRO and EZRadio devices.
How can I calculate the expected range improvement for a given extra link budget?
The range improvement can be calculated based on the following formula:
- ΔR is the desired value of range improvement (ratio between the new and original range)
- n is the propagation factor (the typical outdoor value is between 2.8 and 4)
- ΔLB is the link budget improvement
The ΔLB link budget improvement can be achieved with higher conducted output power, better conducted sensitivity, or with higher antenna gain either on TX or RX side.
Let’s see an example:
Assuming a ΔLB = 3 dB additional link budget improvement (e.g. the TX power is increased or RX sensitivity is improved by 3 dB) and outdoor line of sight between the transmitter and the receiver (which results ~n = 3 propagation factor), the range improvement will be the following:
Thus, for example assuming 400m original range, 3 dB higher transmitter power or 3 dB better sensitivity would result ~500m range.
How can I further reduce the output power level of Si4010?
The guaranteed output power level range of the Si4010 RF transmitter IC is between +10 and -13 dBm. This power output range can be covered by the settings of PA_Power_Level (bLevel) and PA_Max_Drive (bMaxDrv) API registers included in the vPA_Setup() function. The minimum, -13 dBm, output power level can be achieved with bLevel=0 and bMaxDrv=0.
However, the Si4010 RF chip is capable to transmit with a lower power output than -13 dBm. For this, the PA_LVL SFR has to be directly written. The address of the PA_LVL SFR is 0xCE. For a more detailed register description please refer to the "SFR Definition 12.1. PA_LVL" section in the Si4010 datasheet.
After the vPA_Setup() function in the code the PA slice and bias settings can be overwritten by writing the PA_LVL SFR. For reference, the bLevel=0 and bMaxDrv=0 API settings are equivalent with the PA_LVL SFR value of 0x32. Smaller value of this SFR will provide lower power output than -13 dBm.