Question

Why are Si41xx-BM and Si41xx-BT devices unavailable for order?

Answer

Per Process Change Notice #0501071 dated effective 07JAN05, the lead finish version RF Synthesizers were replaced by lead free versions.  So for example, P/Ns Si4133-BM and Si4133-BT were replaced by Si4133-D-GM and Si4133-D-GT.
 

Question

Why is the Si4133W unavailable for order?

Answer

The Si4133W RF Synthesizer, i.e. the wide temperature operation version of the Si4133, was sold as a product line by Silicon Labs to NXP as part of the Aerophone technology sale in 2007.  NXP then briefly sold it as the Aero4133, discontinuing it at the end of 2008.

Question

If the LDETB signal cannot be used as a PLL settling indicator, what approach should one take?

Answer

As noted in RF Synthesizer Knowledge Base article LDETB signal as PLL settling indicator (90292), the LDETB signal should not be solely relied on as a PLL settling indicator.  This is because it also serves to indicate the PLL is about to lose lock due to temperature drift.  Therefore LDETB can be asserted before the PLL has sufficiently settled in an application, e.g. to within 0.1 ppm of the settled final frequency.

The best approach is to allow for the maximum settling time and then check LDETB. The Si4133 datasheet (Rev. 1.61 as of this writing) for example gives the following guidance regarding settling time:

 

The settling time for the PLL is directly proportional to its phase detector update period TΦ (TΦ equals 1/fΦ). A typical transient response is shown in Figure 6 on page 11. During the first 13 update periods the Si4133 executes the self-tuning algorithm. From then on the PLL controls the output frequency. Because of the unique architecture of the Si4133 PLLs, the time required to settle the output frequency to 0.1 ppm error is automatically 25 update periods. The total time after powerup or a change in programmed frequency until the synthesized frequency is settled—including time for self-tuning—is approximately 40 update periods.

 

Note: The settling time analysis holds for RF1 fΦ > 500 kHz.

Testing should be employed to confirm the worst case settling time for the worst case update rate in any particular application.

Question

What is the Si4133's thermal performance?

Answer

 The Si4133 TSSOP thermal details are as follows: 

  ● Max TJ             = 125 °C 

  ● Theta ja (qJA) = 79.9 °C/W 

  ● Theta jc (qJC) = 16.8 °C/W

The thermal resistances are based on simulation assuming natural convection only.  This information applies to the derivative RF Synthesizer products such as the Si4126 also. 

We expect the QFN package to be superior thermally. While we don't have any specific Si41xx QFN thermal data we do have some generic thermal data for the 28 lead 5x5 mm MLP. In this case, the qJAis calculated to be 34.8 °C/W.

Question

How is the Si4133-D-GT RF Synthesizer marked on the top of the package?

Answer

A popular RF Synthesizer is the Si4133 in the 24-pin TSSOP package.  The orderable P/N is the Si4133-D-GT. However, the “D” representing Revision D is not in the first line of the top part marking. There are also a number of other symbols and abbreviations which this RF Synthesizer Knowledge Base article will explain.

Looking at the image attached to this article, Example_Si4133-D-GT_top_marking.png, there are 3 lines of text and/or symbols as follows:

(1)   The first line reads “Si4133-GT”which signifies the24-pin TSSOP version Si4133.

(2)   The second line is the assembly trace code and reads, in this example, “1021DCF0MT”.

·         The first 4 numbers represent the date code in YYWW format where YY = year, WW = work week

In this example, the device is dated 2010, work week 21.

·         The 1st character after the date code, e.g. “D”, represents the device revision.

·         The 2nd character after the date code, e.g. “C”, represents the fabrication site.

·         The 3rd character after the date code, e.g. “F”, represents the assembly site.

·         The 4th character after the date code is optional and reserved for internal use.

·         The final 5th and 6th characters after the date code are for serialization.

(3)   The third line contains an oval with an “e3” followed by the abbreviation “MY”. 

·         The “e3” in an oval is the JEDEC marking used to designate the category of Pb-Free terminal finish used on the device.  In this case, “e3” = Sn or Matte Tin. 

·         The “MY” refers to the country of origin which in this case is Malaysia.

Question

What is the format of the tuning word?

Answer

AN31 “Inductor Design for the Si41xx Synthesizer Family” describes how to read an 18 bit value from the serial interface which contains the tuning code.  However, the tuning word (coarse varactor) range is only 0 to 0x7FF (11 bits).  The nominal value will vary from board to board depending on the manufacturing tolerance of both the RF Synthesizer and the external tuning inductor.

The coding is as follows: 

Maximum capacitance is all bits on.  The MSB represents slightly less than half the total capacitance (perhaps 5% less).  The next bit represents less than half the remaining capacitance, and so on, excepting the least two bits which are 2:1.   

Question

Where are the datasheets for the Si4112, Si4113, Si4122, and Si4123 devices?

Answer

Question

What is the recommended soldering temperature profile for the Si41xx product family?

Answer

Silicon Laboratories recommends following the JEDEC specification JEDEC-STC-020C.  This is available at www.jedec.org.

Question

What is the Lead Finish on the Synthesizer package?

Answer

All of our synthesizer products are available in lead-free, RoHS-compliant packages. These parts have a 10um thick Matte Tin surface finish that is annealed for 1 hour @ 150C to mitigate tin whisker formation. In addition, we continue to offer our synthesizers with a Sn85/Pb15 solder finish to support our customer's legacy applications.

Question

What is the minimum wait time between power-up and the first register write to the synthesizer?

Answer

Registers may be written to the serial port once the supply voltage reaches the minimum supply voltage as specified in the datasheet.   

Ensure that the input voltage to the serial port does not exceed Vdd + 0.3 volts as specified in the datasheet.