How are GPIO interrupts on the EM3xx SoC platform handled when they arrive in ATOMIC() context?
In the Ember HAL, as used on the EM3xx SoCs, the ATOMIC(...) macro is used to temporarily disable interrupts during execution of the enclosed code statements. However, what happens if an external interrupt (via IRQ pin) is triggered while interrupts are disabled? Is the IRQ interrupt lost? The short answer is No, and this applies to both edge-triggered and level-triggered interrupts.
Let's examine why not:
An edge-sensitive interrupt would cause the pending interrupt flag for the IRQ to be set. This flag will be held (asserted), and then the enabling of said flag is what would allow that signal to propagate. The ATOMIC() block, as defined by the Ember HAL, puts shifts around the priority encoding of the interrupts such that the NVIC wouldn't service said interrupt until the ATOMIC block changes BASEPRI so the event propagates. That means the interrupt would be serviced effectively before the next line of code that immediately follows the ATOMIC() block.
A level-triggered interrupt would behave the same way even if, by the time ATOMIC() block finishes, the level has changed. This is becausethe event gets latched in the NVIC and serviced when the BASEPRI says it can be.