What is the optimum termination impedance for the EM35x RF chips? How does its matching network look?
The optimum load at the PA on the silicon die is approximately 700 Ω when the PA/LNA device capacitance is resonated-out. This maximizes the voltage swing at the drains of the PA devices within the available supply voltage.
However, the optimum load presented to the pins of the EM35x SOC must take into consideration not only the optimum PA load but also on-chip parasitic capacitance and package bond-wire inductance. It is estimated that the optimum load presented to the pins is 27 + j95 Ω (series impedance). This is equivalent to a parallel resistance of 368 Ω combined with a parallel inductance of 6.6nH.
Now, the question is: how to match it to achieve the best possible RF performance?
The term “matching” typically implies conjugate power matching. It is important to understand that the EM35x PA is not power matched according to the traditional definition. The term is applied to describe designing to optimal PA impedance.
PCB parasitics play a part in the impedance transformation and that, even with the tightest of layouts, traces between the matching elements will add significant reactance at 2.4 GHz. In particular, there will be some series inductance between the package pins and the first matching element. This is significant when that element is in shunt because it cannot be absorbed into that reactance. Since this effect cannot be avoided, it is best to take advantage of it.
The lowest loss, least complex arrangement is series inductance followed by shunt inductance. To make use of the PCB traces it must be recognized that they operate more like transmission lines, which travel slightly differently on the Smith chart compared with real inductors and this affects the shunt inductance value.
To summarize, the matching network includes:
- only one parallel inductor between the RF pins, typical value is between 2.7 and 3.9 nH
- PCB traces between the EM35x RF chip and the parallel inductor mentioned above
The required differential load impedance at the parallel indcutor pins is pure, real 100 Ω.
So, basically with only one parallel inductor (besides the PCB traces) the RF chip can be matched to pure 100 ohm differential impedance. After that a ceramic balun with filter, a FEM or a differential-type antenna can be directly placed. Or, even a discrete matching balun network with filter can be designed to get a single-ended output. See our reference designs.
But, in all cases the first parallel inductor is required (this can be imagined like it is necessary to resonate out the PA/LNA device capacitance). This inductor also comes handy in the PA biasing, where both RF pins need to be pulled-up to VDD. The suggested RF choke inductor value is 22 nH (shows high impedance at the fundamental frequency) what is connected between the VDD and RF path.
For more details please refer to the AN698 Application note and see our reference design schematics and layouts. If any questions, you may submit them along with your schematic design files to the support portal and request a review by the Wireless Hardware Support Team before finalizing your PCB layout design in order to make sure any concerns are resolved and the key design elements are included, especially important for some custom designs meant for high temperature applications, have reduced layer stack counts or are space constrained. When submitting a design for review, please also submit a completed Hardware Design Review Questionnaire to assist the support team in providing the most appropriate and comprehensive response.
Link to the EM35xx Hardware Design Review Questionnaire: