Below is a list of the most common design review feedback items for EM35x customer design reviews. Before you complete your EM35x-based design and submit design files for review by our support team, please review this list and refer to the documentation links below.
The nRESET pin has an internal glitch filter and pull-up and should not have external filters or pull-up components attached, as they can negatively affect the overall stability of nRESET. For more information refer to the EM357 datasheet section 6.2.1.2. NRESET Pin.
Verify the 24 MHz crystal case is not grounded in order to keep the crystal loop currents which are absorbed by the case from coupling into the EM35x reference ground. These loop currents can be at frequencies which impact the IF and RF as noise. Note an exception is known for when the EM35x is referenced to a floating ground whereby custom PCB topology results in near field noise coupling onto the floating crystal case, such as from a switching power supply. In this rare situation, the problem can be solved by grounding the crystal case.
The 1V8 PCB power route should be connected serially from the source via to decoupling capacitor and then to target EM35xx pin for better noise suppression. Source vias which are placed between the decoupling capacitor and the target IC power pin results in reduced noise immunity for the power pin.
1.8V net routing should be star-routed to take advantage of the inductive impedance resulting from creating longer trace lengths to provide filtering to individual power pins without having to add external ferrite bead components at each IC power pin as they are more expensive. If star routing is not followed, then it results in reduced noise immunity and the chances of noise coupling to the power pins increases.
Each decoupling capacitor ground pad should have its own separate via to the EM35x reference ground plane and not be attached to the top layer plane ground plane or share vias between two or more capacitors in order to reduce the potential for noise to couple into the EM35X power pin being decoupled. Refer to AN698 for more details: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN698.pdf
Crystal loading caps should share same ground via to make the crystal loop currents as short as possible and to prevent them from coupling onto the EM35x reference ground plane and/or nearby power and signal traces.
The filtering capacitor for EM35x pins 5 (VDD_RF), 8 (VDD_IF) and the RF differential port DC bias pin(s) should be 8 pF to 10 pF because they have resonating frequency of 2.4 GHz.
Verify the 24 MHz crystal tuning capacitor values. Note the values may vary according to the crystal specification however they must be symmetrical. Verify crystal value as per the application note AN700, section 2.6. See the following link: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN700.pdf.
Create pastemask layer window openings within the ground slug pad area of Em35xx as they are necessary for properly creating the solder stencil used in the assembly process. Refer datasheet section 20 for more details. http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x.pdf
Hi, In one of my application project,I need EM357 module with SE2432 .SoI took same reference design given by silicon labs with same Gerber file and PCB design files for fabrication.But from fabrication I got issues regarding EM357 Gerber files that 1.Tented vias are required 2.solder mask is required as I am new to PCB software ,kindly see and resolve my issue.
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Tented vias and / or soldermask over vias is optional but is generally recommended by PCB fabricators to prevent acidic and corrosive chemicals that are sometimes used during PCA assembly from being trapped inside the via, which could then result in circuit disconnects over time due to corrosion of the copper. Additionally, some of the vias in the design mentioned are located underneath the QFN components. The concern by the PCB fabricator for these vias is that solder can weep through the vias from the component side to the other side of the PCB and potentially create solder balls which can become dislodged and short circuit other exposed circuits.
To tent or to have solder mask placed on the vias in your design, simply place a fabrication note instructing your PCB fabricator to use either method for all exposed vias in the design.
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Dear Sir, I used same reference design which is silicon labs website,but when I send Gerber files to fabrication.I got 3 comments from fabricator that tented vias and red solder mask is required on bottom layer and one more is 1Mil trace is there where copper pouring is required. Looking forward for your reply. Thanks and Regards, Dinesh katkar
EM35x - Most Common Design Review Feedback
Tented vias and / or soldermask over vias is optional but is generally recommended by PCB fabricators to prevent acidic and corrosive chemicals that are sometimes used during PCA assembly from being trapped inside the via, which could then result in circuit disconnects over time due to corrosion of the copper. Additionally, some of the vias in the design mentioned are located underneath the QFN components. The concern by the PCB fabricator for these vias is that solder can weep through the vias from the component side to the other side of the PCB and potentially create solder balls which can become dislodged and short circuit other exposed circuits.
To tent or to have solder mask placed on the vias in your design, simply place a fabrication note instructing your PCB fabricator to use either method for all exposed vias in the design.
Hello Dinesh,
To resolve this issue, we recommend you submit a technical support request at https://siliconlabs.force.com.
Thank you and best regards.