Within EmberZNet and Silicon Labs Thread, different sleep modes are supported based on the particular chip you have selected for your product. This KBA will outline the different sleep modes within EM35x and EFR32 chips and how they are used within the stack.
When utilizing Silicon Labs wireless mesh stacks, the EM35x supports two different sleep modes: Deep Sleep and Power Down. Both of these modes will get down to under 1 µA of current, with Power Down being able to realize lower current consumption.
This is the primary sleep mode of the EM35x. In this mode the EM35x will go into a lower current sleep mode by halting most peripherals, maintaining the ability to wake due to GPIO interrupts or a wake timer. This means that the EM35x can be woken by an external event, like a button press, or a scheduled event that is pending, such as polling event scheduled at set intervals.
This is the only supported sleep mode of any EM35x SoC design, utilizing the Idle/Sleep plugin, while it is one of two sleep modes that are supported by an EM35x NCP design, utilizing the sleep bits of the Frame Control bytes within the EZSP structure (see UG100: EZSP Reference Guide for full details).
This is a secondary sleep mode of the EM35x. In this mode the EM35x will go into a lower current sleep mode by halting most peripherals, including all timers as well. In this state only a GPIO interrupt can wake the EM35x.
This sleep mode is only supported in the EM35x NCP design as timer functionality can be offloaded to the Host processor, which can trigger polling or other scheduled events, utilizing the external interrupt to wake the NCP. This mode can be entered by utilizing the sleep bits of the Frame Control bytes within the EZSP structure (see UG100: EZSP Reference Guide for full details).
Within EmberZNet and Silicon Labs Thread, the EFR32 can support two different sleep modes as well.
This is the primary sleep mode utilized by the wireless mesh stacks on the EFR32. In this mode the EFR32 will halt most peripherals and many timers, keeping only system necessary timers running. In this mode, the EFR32 maintains the ability to wake due to all interrupts or a wake timer and will resume operation as normal when waking from sleep.
To utilize this within an SoC design, use of the Idle/Sleep plugin is necessary. EM2 sleep can be utilized on SPI based NCP implementations through the sleep bits of the Frame Control bytes within the EZSP structure (see UG100: EZSP Reference Guide for full details).
EM4 is a special use case sleep mode that disables most functionality within the EFR32 and puts it into a hibernation state. In this mode the EFR32 can only be woken via a select GPIO wake mask or a system timer. Wake in this mode is treated like a reset of the processor.
To utilize EM4 sleep, you will need to enable the EM4 plugin with your application. You will need to further enable the emberAfOKToGoToEM4Callback() within your application’s callbacks. Within this function, you will enable the logic for which your application will enter into EM4 sleep.
NOTE: EM4 sleep is highly disruptive within normal operation of the stack. Use of it can result in an application that will have difficulty meeting Zigbee or Thread certification. It should only be utilized when this extremely low power mode is required and a well-defined state machine handling the sleep mode of the stack can be defined to govern the EFR32’s behavior.