The EFR32 families of chips each come equipped with multiple Power Amplifiers (PAs):
EFR32xG1x
A high-power * 2.4 GHz PA (for power 20 dBm and lower)**
A low-power 2.4 GHz PA (for power 0 dBm and lower)
A Sub-GHz PA**
EFR32xG21
A high-power 2.4 GHz PA (for power 20 dBm and lower)**
A medium-power 2.4 GHz PA (for power 10 dBm and lower)
A low-power 2.4 GHz PA (for power 0 dBm and lower)
EFR32xG22
A high-power 2.4 GHz PA (for power 6 dBm and lower)**
A low-power 2.4 GHz PA (for power 0 dBm and lower)
Each of these PAs has a unique number of discrete “power levels”, which are simply abstractions of the different register settings that control the active PA. For each PA, the following power levels are available:
EFR32xG1x
High-power 2.4 Ghz: 0-252**
Low-power 2.4 Ghz: 1-7
Sub-GHz: 0-248
EFR32xG21
High-power 2.4 Ghz: 1-180**
Medium-power 2.4 Ghz: 1-90
Low-power 2.4 Ghz: 1-64
EFR32xG22
High-power 2.4 Ghz: 0-128**
Low-power 2.4 Ghz: 0-15
*Note that the use of 'high', 'medium', and 'low' in the names of these PAs refers to power consumption, not power output. It is possible, for instance, to configure the high-power PA to transmit at a lower dBm output than the low-power PA.
**Maximum power/use of these PAs may be restricted by your specific OPN. Please see the data sheet for more details regarding your particular part.
The purpose of this KBA is to organize all Wireless Hardware related specific/generic technical documents (application notes and KBAs) applicable to EFR32 Series 2 SoCs and Wireless modules in one place. The content is grouped into the following categories to make it easier to find what you are looking for.
BSDL files do not exist for EFR32 devices, because there is no boundary-scan TAP in the EFR32. We do have the ARM SWJ-DP which handles JTAG/SWD based accesses to the debug port (DP).
What is the typical power consumption of the Synthesizer?
Answer
For the Si4133, when RF and IF are operating, typical current is 18 mA (See device datasheet Table 3). To calculate power consumption, multiply the current by the operating voltage. Typical power consumption is 3.0 v * 18 mA = 54 mW
When the Synthesizer is powered down, typical current consumption is approximately 1 uA and power consumption is 3 uW.
What are the factors that affect phase noise? Can phase noise be reduced?
Answer
The three main factors that affect phase noise are update rate, phase detector gain and the phase noise characteristic of the reference frequency. Other factors such as the temperature and supply voltage level have a minimal effect on phase noise.
Update Rate:
The update rate is the frequency at which the synthesizer phase detector is operating. Mathematically, it is represented as Update Rate = FREF/R, where FREF is the reference frequency. Generally, the higher the update rate, the lower the phase noise. Figure 1 below shows the phase noise characteristic for Si4133 (IF = 550 MHz) under typical conditions. The update rates used are 200 kHz and 1000 kHz.
Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz
From figure 1 above, it is apparent that the 1000 kHz update rate results in lower phase noise. This is more noticeable at lower offset frequencies.
The update rate also affects the loop bandwidth. This effect can also be observed in figure 1. The loop bandwidth of the synthesizers is proportional to the update rate.
Phase Detector Gain:
The phase detector gain setting can also be used for optimizing phase noise performance. Figure 2 below shows the phase noise characteristics for various RF1 phase detector (KP1) settings.
Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1
For offset frequencies much less than the loop bandwidth, higher phase detector gains lead to lower phase noise. However, it is important to point out that a very large phase detector gain can also result in the loop being unstable. It is recommended that the phase detector gain be set according to the value programmed into the N register. This information is available in the synthesizer device datasheets.
Frequency Reference:
At offset frequencies much less than the loop bandwidth, the reference source largely determines the phase noise of the output. For this reason, it is recommended that a stable reference such as a temperature compensated crystal oscillator (TCXO) be used in applications requiring very good phase noise performance.
In general for synthesizers, the phase noise at a given offset frequency reduces as the offset frequency increases. For integrated phase noise therefore, the lower offset frequencies dominate the integration. As a result, the frequency reference plays a dominant role in the value of the integrated phase error.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
The parameters dependent on, or affected by, the update rate include loop bandwidth, settling time of the PLL, resolution of the channel spacing, and the location of reference related spurs on the phase noise characteristic. Additionally, the loop bandwidth determines the dominant source of phase noise at a given frequency offset.
Loop Bandwidth:
The update rate determines the loop bandwidth of the PLL. Specifically, the loop bandwidth is approximately one tenth of the update rate. Changing the update rate affects the overall phase noise characteristic.
For offset frequencies much less than the loop bandwidth, the overall phase noise is dominated by the reference source. On the other hand, the voltage-controlled oscillator (VCO) phase noise dominates the overall phase noise for offset frequencies much larger than the loop bandwidth.
Settling Time:
The settling time of the PLL is also dependent on the update rate. A higher update rate leads to a shorter settling time. Specific details about the relationship between update rate and settling time are contained in the synthesizer device data sheets. As an example, a 500 kHz update rate on the Si4133 corresponds to a settling time of 80us.
Channel Spacing Resolution:
Resolution of the channel spacing is determined by the update rate. The output frequency can be written as FOUT = (FREF/R)*N, where FREF is the reference frequency. This can be re-written as FOUT = (Update Rate)*N. Therefore, the output frequency can be changed in steps equivalent to the update rate. This is achieved by simply incrementing or decrementing the value of the N register.
Channel spacing is an important consideration in applications where the synthesizer is used to generate different frequencies. A lower update rate is necessary for more closely spaced channels.
Reference Related Spurs:
Reference related spurs are present in the output frequency spectrum of the synthesizer and occur at integer intervals of the update rate. These spurs can be seen in figures 1 and 2 below. In figure 1, update rates of 200 kHz and 1000 kHz are used. In the case of the 200 kHz update rate, the spurs are located at 200kHz, 400kHz, 600kHz and 1000kHz. For the 1000kHz update rate, the first spur is located at an offset of 1000kHz.
Generally, the MLP packages offers better reference related spur performance than TSSOP packages.
Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz
Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
How is extended frequency operation implemented on the Si4133?
Answer
To implement the extended frequency option, the RFLA and RFLB pins should be connected with the shortest trace possible. The extended frequency is available only for on the MLP package of the Si4133 family. In addition, bit D1 of the main configuration register should be set to 1 and VDD set to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Is the lock temperature range fixed or does it shift each time the synthesizer is retuned?
Answer
The lock maintenance range is centered on the ambient temperature in which the retuning or self-tuning algorithm is carried out. For instance, the Si4133 has a 300C lock maintenance range. If the self-tuning algorithm is carried out at 25C, the Si4133 can maintain lock in the -50C to 550C temperature range. If the self-tuning algorithm is carried out at 550C on the other hand, the Si4133 can maintain lock in the in the 250C to 850C temperature range.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
In synthesizers containing both RF1 and RF2 PLLs, how is the active PLL determined?
Answer
The last N or R divider registers written into determines the active RF PLL. For example, if the R divider register for RF1 is programmed, the active RF PLL becomes RF1, and its output is available in the RFOUT output.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
There appears to be a dead-zone between the Si4133 RF1 VCOs normal and extended tuning ranges. What is the effect of operating the RF1 VCO in this range?
Answer
The Si4133 RF1 VCO datasheet limits are 900-1806 MHz and 1850-2050 MHz for the normal and extended frequency operations respectively. Operation in the 1806-1850 MHz range is possible. However, this range falls outside the guaranteed datasheet specifications.
The device should be used in the extended frequency mode. Also, only the MLP package should be used. The extended frequency operation is implemented by setting the D1 bit of the main configuration register to 1 and setting VDD to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers and Application Note 31Inductor Design for the Si41xx Synthesizer Family.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Zigbee & Thread Knowledge Base
What are the valid values for txPower in EFR32 devices?
The EFR32 families of chips each come equipped with multiple Power Amplifiers (PAs):
Each of these PAs has a unique number of discrete “power levels”, which are simply abstractions of the different register settings that control the active PA. For each PA, the following power levels are available:
*Note that the use of 'high', 'medium', and 'low' in the names of these PAs refers to power consumption, not power output. It is possible, for instance, to configure the high-power PA to transmit at a lower dBm output than the low-power PA.
**Maximum power/use of these PAs may be restricted by your specific OPN. Please see the data sheet for more details regarding your particular part.
For more details and to set custom power curves for your design, refer AN1127: Power Amplifier Power Conversion Functions in RAIL 2.x
Master Wireless Hardware Doc list for EFR32 Series 2 SoCs and Wireless Modules
The purpose of this KBA is to organize all Wireless Hardware related specific/generic technical documents (application notes and KBAs) applicable to EFR32 Series 2 SoCs and Wireless modules in one place. The content is grouped into the following categories to make it easier to find what you are looking for.
[A] EFR32 Series 2 Wireless Modules:
Application Notes
AN1048: Regulatory RF Module Certifications
AN1223: LGA Manufacturing Guidance
KBAs
STEP File information and steps to obtain those files
Design and Assembly guidelines for SiPs
[B] EFR32 Series 2 Wireless SoCs:
AN0002.2: EFR32 Wireless Gecko Series 2 Hardware Design Considerations
AN0948.2: EFR32 Series 2 Power Configurations and DC-DC
AN933.2: EFR32 Series 2 Minimal BOM
AN930.2: EFR32 Series 2 2.4 GHz Matching Guide
AN928.2: EFR32 Series 2 Layout Design Guide
[C] Generic
[1] RF
KBAs
ESD protection of RF devices
RF Range calculator
RF Range factors
Range improvement calculation for a given extra link budget
Data rate, deviation, modulation index for 2GFSK signals
Modulation choice
OBW for digital modulations
Modulation index for digital modulations
RF shield vs. RX immunity
General layer count versus power output recommendations
Custom design PCB number of layers
Recommended routing technique for more layer RF designs
General RF layout suggestions
[2] Certifications
KBAs
Maximum allowed power for ZigBee applications under ETSI EN 300 328
ETSI EN 300 328 Adaptivity Compliance
FCC Harmonic Requirements
TX power limitations for regulatory compliance (ETSI, FCC)
Tips for FCC certification on Silicon Labs' 2.4GHz 802.15.4-based solutions
How to test and estimate TIS/TRP
[3] Antenna
Application Notes
AN1088: Designing with an Inverted-F 2.4 GHz PCB Antenna
APL10045: Antennas for Short Range Devices
AN853: Single-ended Antenna Matrix Design Guide
KBAs
Design tip for dipole antennas
Whip antenna length and size
Whip antenna parameters
Do loop antennas require a ground plane?
PCB antenna with wider bandwidth
Recommended distance between antennas for antenna diversity
Recommended external antenna matching network
How to maximize the isolation of coex. antennas on the same PCB
[4] Coexistence
AN1128: Bluetooth® Coexistence with Wi-Fi®
AN1017: Zigbee® and Silicon Labs® Thread Coexistence with Wi-Fi®
[5] MCU/Peripherals
Application Notes
AN958: Debugging and Programming Interfaces for Custom Designs
AN0016.2: Oscillator Design Considerations
KBAs
EFR32 DCDC powering external circuits
BSDL files
Layout design practices around DC-DC converter
CTUNE Access
HFXO Capacitor Bank (Ctune) calibration on EFR32
Saving CTUNE value as manufacturing token
[6] Testing
Application Notes
AN972: EFR32 RF Evaluation Guide
AN718: Manufacturing Test Overview
AN700.1: Manufacturing Test Guidelines for the EFR32
AN1162: Using the Manufacturing Library for EmberZNet
AN1046: Radio Frequency Physical Layer Evaluation in Bluetooth® SDK v2.x
AN1267: Radio Frequency Physical Layer Evaluation in Bluetooth® SDK v3.x
UG409: RAILtest User’s Guide
AN1019: Using the NodeTest Application
AN961: Bringing Up Custom Devices for the EFR32MG and EFR32FG Families
KBAs
How to build and use the StandardizedRfTesting sample in EmberZnet SDK?
Implementing wireless direct test mode (DTM)
[7] Other
How do I determine the PCB and schematic version of kit boards?
BRD4001A WSTK dimension
Hardware Design Review submission expectations for EFR32MGxx based designs
What are the valid values for txPower?
How to find schematics and other documentation for radio boards?
Six Hidden Costs in a Wireless SoC Design
Where can I find BSDL file for EFR32 Wireless Gecko devices?
Synthesizer Power Consumption
Question
What is the typical power consumption of the Synthesizer?
Answer
For the Si4133, when RF and IF are operating, typical current is 18 mA (See device datasheet Table 3). To calculate power consumption, multiply the current by the operating voltage. Typical power consumption is 3.0 v * 18 mA = 54 mW
When the Synthesizer is powered down, typical current consumption is approximately 1 uA and power consumption is 3 uW.
Phase noise overview
Question
What are the factors that affect phase noise? Can phase noise be reduced?
Answer
The three main factors that affect phase noise are update rate, phase detector gain and the phase noise characteristic of the reference frequency. Other factors such as the temperature and supply voltage level have a minimal effect on phase noise.
Update Rate:
The update rate is the frequency at which the synthesizer phase detector is operating. Mathematically, it is represented as Update Rate = FREF/R, where FREF is the reference frequency. Generally, the higher the update rate, the lower the phase noise. Figure 1 below shows the phase noise characteristic for Si4133 (IF = 550 MHz) under typical conditions. The update rates used are 200 kHz and 1000 kHz.
Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz
From figure 1 above, it is apparent that the 1000 kHz update rate results in lower phase noise. This is more noticeable at lower offset frequencies.
The update rate also affects the loop bandwidth. This effect can also be observed in figure 1. The loop bandwidth of the synthesizers is proportional to the update rate.
Phase Detector Gain:
The phase detector gain setting can also be used for optimizing phase noise performance. Figure 2 below shows the phase noise characteristics for various RF1 phase detector (KP1) settings.
Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1
For offset frequencies much less than the loop bandwidth, higher phase detector gains lead to lower phase noise. However, it is important to point out that a very large phase detector gain can also result in the loop being unstable. It is recommended that the phase detector gain be set according to the value programmed into the N register. This information is available in the synthesizer device datasheets.
Frequency Reference:
At offset frequencies much less than the loop bandwidth, the reference source largely determines the phase noise of the output. For this reason, it is recommended that a stable reference such as a temperature compensated crystal oscillator (TCXO) be used in applications requiring very good phase noise performance.
In general for synthesizers, the phase noise at a given offset frequency reduces as the offset frequency increases. For integrated phase noise therefore, the lower offset frequencies dominate the integration. As a result, the frequency reference plays a dominant role in the value of the integrated phase error.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Update rate effects
Question
What are the effects of changing the update rate?
Answer
The parameters dependent on, or affected by, the update rate include loop bandwidth, settling time of the PLL, resolution of the channel spacing, and the location of reference related spurs on the phase noise characteristic. Additionally, the loop bandwidth determines the dominant source of phase noise at a given frequency offset.
Loop Bandwidth:
The update rate determines the loop bandwidth of the PLL. Specifically, the loop bandwidth is approximately one tenth of the update rate. Changing the update rate affects the overall phase noise characteristic.
For offset frequencies much less than the loop bandwidth, the overall phase noise is dominated by the reference source. On the other hand, the voltage-controlled oscillator (VCO) phase noise dominates the overall phase noise for offset frequencies much larger than the loop bandwidth.
Settling Time:
The settling time of the PLL is also dependent on the update rate. A higher update rate leads to a shorter settling time. Specific details about the relationship between update rate and settling time are contained in the synthesizer device data sheets. As an example, a 500 kHz update rate on the Si4133 corresponds to a settling time of 80us.
Channel Spacing Resolution:
Resolution of the channel spacing is determined by the update rate. The output frequency can be written as FOUT = (FREF/R)*N, where FREF is the reference frequency. This can be re-written as FOUT = (Update Rate)*N. Therefore, the output frequency can be changed in steps equivalent to the update rate. This is achieved by simply incrementing or decrementing the value of the N register.
Channel spacing is an important consideration in applications where the synthesizer is used to generate different frequencies. A lower update rate is necessary for more closely spaced channels.
Reference Related Spurs:
Reference related spurs are present in the output frequency spectrum of the synthesizer and occur at integer intervals of the update rate. These spurs can be seen in figures 1 and 2 below. In figure 1, update rates of 200 kHz and 1000 kHz are used. In the case of the 200 kHz update rate, the spurs are located at 200kHz, 400kHz, 600kHz and 1000kHz. For the 1000kHz update rate, the first spur is located at an offset of 1000kHz.
Generally, the MLP packages offers better reference related spur performance than TSSOP packages.
Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz
Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Si4133 extended frequency range operation
Question
How is extended frequency operation implemented on the Si4133?
Answer
To implement the extended frequency option, the RFLA and RFLB pins should be connected with the shortest trace possible. The extended frequency is available only for on the MLP package of the Si4133 family. In addition, bit D1 of the main configuration register should be set to 1 and VDD set to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Lock temperature range dependence on self-tuning ambient temperature
Question
Is the lock temperature range fixed or does it shift each time the synthesizer is retuned?
Answer
The lock maintenance range is centered on the ambient temperature in which the retuning or self-tuning algorithm is carried out. For instance, the Si4133 has a 300C lock maintenance range. If the self-tuning algorithm is carried out at 25C, the Si4133 can maintain lock in the -50C to 550C temperature range. If the self-tuning algorithm is carried out at 550C on the other hand, the Si4133 can maintain lock in the in the 250C to 850C temperature range.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
RF1/RF2 active PLL determination
Question
In synthesizers containing both RF1 and RF2 PLLs, how is the active PLL determined?
Answer
The last N or R divider registers written into determines the active RF PLL. For example, if the R divider register for RF1 is programmed, the active RF PLL becomes RF1, and its output is available in the RFOUT output.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.
Frequency gap between normal and extended ranges of the Si4133 RF1 PLL
Question
There appears to be a dead-zone between the Si4133 RF1 VCOs normal and extended tuning ranges. What is the effect of operating the RF1 VCO in this range?
Answer
The Si4133 RF1 VCO datasheet limits are 900-1806 MHz and 1850-2050 MHz for the normal and extended frequency operations respectively. Operation in the 1806-1850 MHz range is possible. However, this range falls outside the guaranteed datasheet specifications.
The device should be used in the extended frequency mode. Also, only the MLP package should be used. The extended frequency operation is implemented by setting the D1 bit of the main configuration register to 1 and setting VDD to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers and Application Note 31 Inductor Design for the Si41xx Synthesizer Family.
For related questions, refer to the “Related Articles” section located to the right of this question.
For further technical assistance, please click on the “Technical Info” link. For sales information, please click on the “Sales Info” link. Both of these links are located to the right of this question.