Question

 

What is the typical power consumption of the Synthesizer?

 

Answer

 

 

For the Si4133, when RF and IF are operating, typical current is 18 mA (See device datasheet Table 3).  To calculate power consumption, multiply the current by the operating voltage.  Typical power consumption is 3.0 v * 18 mA = 54 mW

 

 

 

When the Synthesizer is powered down, typical current consumption is approximately 1 uA and power consumption is 3 uW.

 

Question

 

What are the factors that affect phase noise? Can phase noise be reduced?

 

Answer

 

 

The three main factors that affect phase noise are update rate, phase detector gain and the phase noise characteristic of the reference frequency. Other factors such as the temperature and supply voltage level have a minimal effect on phase noise.

 

 

 

Update Rate:

 

 

 

The update rate is the frequency at which the synthesizer phase detector is operating. Mathematically, it is represented as Update Rate = FREF/R, where FREF is the reference frequency. Generally, the higher the update rate, the lower the phase noise. Figure 1 below shows the phase noise characteristic for Si4133 (IF = 550 MHz) under typical conditions. The update rates used are 200 kHz and 1000 kHz.

 

 

 

 

Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz

 

 

 

From figure 1 above, it is apparent that the 1000 kHz update rate results in lower phase noise. This is more noticeable at lower offset frequencies.

 

 

 

The update rate also affects the loop bandwidth. This effect can also be observed in figure 1. The loop bandwidth of the synthesizers is proportional to the update rate.

 

 

 

Phase Detector Gain:

 

 

 

The phase detector gain setting can also be used for optimizing phase noise performance. Figure 2 below shows the phase noise characteristics for various RF1 phase detector (KP1) settings.

 

 

 

 

 

Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1

 

 

 

For offset frequencies much less than the loop bandwidth, higher phase detector gains lead to lower phase noise. However, it is important to point out that a very large phase detector gain can also result in the loop being unstable. It is recommended that the phase detector gain be set according to the value programmed into the N register. This information is available in the synthesizer device datasheets.

 

 

 

 

 

 

 

 

 

Frequency Reference:

 

 

 

At offset frequencies much less than the loop bandwidth, the reference source largely determines the phase noise of the output. For this reason, it is recommended that a stable reference such as a temperature compensated crystal oscillator (TCXO) be used in applications requiring very good phase noise performance.

 

 

 

In general for synthesizers, the phase noise at a given offset frequency reduces as the offset frequency increases. For integrated phase noise therefore, the lower offset frequencies dominate the integration. As a result, the frequency reference plays a dominant role in the value of the integrated phase error.

 

 

 

 

 

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Question

 

 

What are the effects of changing the update rate?

 

Answer

 

 

The parameters dependent on, or affected by, the update rate include loop bandwidth, settling time of the PLL, resolution of the channel spacing, and the location of reference related spurs on the phase noise characteristic. Additionally, the loop bandwidth determines the dominant source of phase noise at a given frequency offset.

 

 

 

Loop Bandwidth:

 

 

 

The update rate determines the loop bandwidth of the PLL. Specifically, the loop bandwidth is approximately one tenth of the update rate. Changing the update rate affects the overall phase noise characteristic.

 

 

 

For offset frequencies much less than the loop bandwidth, the overall phase noise is dominated by the reference source. On the other hand, the voltage-controlled oscillator (VCO) phase noise dominates the overall phase noise for offset frequencies much larger than the loop bandwidth.

 

 

 

Settling Time:

 

 

 

The settling time of the PLL is also dependent on the update rate. A higher update rate leads to a shorter settling time. Specific details about the relationship between update rate and settling time are contained in the synthesizer device data sheets. As an example, a 500 kHz update rate on the Si4133 corresponds to a settling time of 80us.

 

 

 

Channel Spacing Resolution:

 

 

 

Resolution of the channel spacing is determined by the update rate. The output frequency can be written as FOUT = (FREF/R)*N, where FREF is the reference frequency. This can be re-written as FOUT = (Update Rate)*N. Therefore, the output frequency can be changed in steps equivalent to the update rate. This is achieved by simply incrementing or decrementing the value of the N register.

 

 

 

Channel spacing is an important consideration in applications where the synthesizer is used to generate different frequencies. A lower update rate is necessary for more closely spaced channels.

 

 

 

 

 

Reference Related Spurs:

 

 

 

Reference related spurs are present in the output frequency spectrum of the synthesizer and occur at integer intervals of the update rate.  These spurs can be seen in figures 1 and 2 below. In figure 1, update rates of 200 kHz and 1000 kHz are used. In the case of the 200 kHz update rate, the spurs are located at 200kHz, 400kHz, 600kHz and 1000kHz. For the 1000kHz update rate, the first spur is located at an offset of 1000kHz.

 

 

 

 

Generally, the MLP packages offers better reference related spur performance than TSSOP packages.

 

 

 

 

Fig 1: Si4133 Phase Noise for Fphi = 200 kHz and 1000 kHz

 

 

 

 

 

 

 

 

Figure 2: Si4133 Phase Noise for KP1 = 1/8, 1/4, 1/2 and 1

 

 

 

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Question

 

What are the phase noise characteristics of the synthesizers?

 

Answer

 

 

The phase noise specifications for each synthesizer are contained in the respective device datasheets. For example, the typical phase noise of the Si4133 RF2 PLL operating at 1.2GHz is -134 dBc/Hz at a 1 MHz offset. The integrated phase error under the same conditions (from 10 Hz to 100 kHz) is 0.7 degrees rms.

 

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Question

 

How is extended frequency operation implemented on the Si4133?

 

Answer

 

 

To implement the extended frequency option, the RFLA and RFLB pins should be connected with the shortest trace possible. The extended frequency is available only for on the MLP package of the Si4133 family. In addition, bit D1 of the main configuration register should be set to 1 and VDD set to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers.

 

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Question

 

Is the lock temperature range fixed or does it shift each time the synthesizer is retuned?

 

Answer

 

 

The lock maintenance range is centered on the ambient temperature in which the retuning or self-tuning algorithm is carried out. For instance, the Si4133 has a 300C lock maintenance range. If the self-tuning algorithm is carried out at 25C, the Si4133 can maintain lock in the -50C to 550C temperature range. If the self-tuning algorithm is carried out at 550C on the other hand, the Si4133 can maintain lock in the in the 250C to 850C temperature range.

 

 

 

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Question

 

There appears to be a dead-zone between the Si4133 RF1 VCOs normal and extended tuning ranges. What is the effect of operating the RF1 VCO in this range?

 

Answer

 

 

The Si4133 RF1 VCO datasheet limits are 900-1806 MHz and 1850-2050 MHz for the normal and extended frequency operations respectively. Operation in the 1806-1850 MHz range is possible. However, this range falls outside the guaranteed datasheet specifications. 

 

 

 

The device should be used in the extended frequency mode. Also, only the MLP package should be used. The extended frequency operation is implemented by setting the D1 bit of the main configuration register to 1 and setting VDD to between 3.0 and 3.6V. For more details, refer to Application Note 41 Extended Frequency Operation of Silicon Laboratories Radio Frequency Synthesizers and Application Note 31 Inductor Design for the Si41xx Synthesizer Family.

 

 

 

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Question

 

Does the synthesizer have any special layout considerations?

 

Answer

 

 

For synthesizers requiring external inductances, refer to Application Note 31 – Inductor Design for the Si41xx Synthesizer Family for details on how to implement the external inductors. A rule of thumb is to use discrete inductors if the required external inductance is greater than 3 nH.

 

 

 

Inductance values for chip inductors progress in discrete steps. To implement specific inductances therefore, a combination of both PCB and trace inductances may be required. 

 

 

 

Precautions should be taken to isolate the reference frequency input trace, the RF output traces, and the inductor traces from potential sources of interference or coupling. The Si4133/33G-EVB datasheet contains layouts for various evaluation boards.

 

 

 

Good grounding techniques should be employed to minimize unwanted signal coupling. This involves ensuring that each RF signal has a continuous ground return path back to its source. The return path should closely follow the sourcing signal’s trace. For MLP packages, connect the ground paddle located in the center of the package to PCB ground. The VDD supply of the synthesizer should be locally bypassed as close to the part as possible. Refer to the “Typical Applications Circuit” diagram in the synthesizer device datasheet for the recommended bypass capacitance.

 

 

 

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Question

 

 

What are the ambient and lock temperature ranges of the Silicon Laboratories synthesizers?

 

Answer

 

 

The table below summarizes both the ambient and lock temperature ranges. The lock temperature range is formed around the ambient temperature in which the self-tuning algorithm is run.

 

Device	Ambient Temperature	Lock Maintenance	Large LDETB
	Range (TA)	Temperature Range	Warning Window
Si4113G-X5	-200C to +850C	300C	NO
Si4114G	-200C to +700C	300C	NO
Si4115G	-200C to +850C	300C	NO
Si4133/23/22/13/12	-400C to +850C	300C	NO
Si4133-X1	-400C to +850C	300C	NO
Si4133G/23G/22G/13G/12G	-200C to +850C	300C	NO
Si4133G-X2	-200C to +850C	300C	NO
Si4133W	-250C to +850C	-500C to +800C	YES
Si4126/36	-400C to +850C	300C	YES
Si4136XM	-400C to +850C	300C	YES

 

 

 

 

 

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