This document provides API descriptions for the commands and properties used
to control and configure the part. The interface version tracks any functional
changes to the API (command, property, field, enumeration, etc.). The documentation
version tracks any text changes to the summary or description text of the API
components.
The commands are listed in a summary table with links to command details.
The properties are listed in a summary
table with links to property details. The feature available column in the
summary tables lists the firmware revision which first implemented the command
or property.
An entry in the summary table will link
to a details section, which contains a register view with fields. Clicking a
field in the register view will auto-expand the corresponding field details.
An up button in the field detail links back to the register view. Each
register view title links back to the summary table entry. These hyper-links
provide two-click access from top to bottom.
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COMMON_COMMANDS | |||
---|---|---|---|---|
Number | Name | Summary | Feature Available | |
0x00 | NOP | No Operation command. | ||
0x01 | PART_INFO | Reports basic information about the device. | ||
0x10 | FUNC_INFO | Returns the Function revision information of the device. | ||
0x11 | SET_PROPERTY | Sets the value of one or more properties. | ||
0x12 | GET_PROPERTY | Retrieves the value of one or more properties | ||
0x13 | GPIO_PIN_CFG | Configures the GPIO pins. | ||
0x15 | FIFO_INFO | Access the current byte counts in the TX and RX FIFOs, and provide for resetting the FIFOs. | ||
0x20 | GET_INT_STATUS | Returns the interrupt status of ALL the possible interrupt events (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. | ||
0x33 | REQUEST_DEVICE_STATE | Request current device state and channel. | ||
0x34 | CHANGE_STATE | Manually switch the chip to a desired operating state. | ||
0x44 | READ_CMD_BUFF | Used to read CTS and the command response. | ||
0x50 | FRR_A_READ | Reads the fast response registers (FRR) starting with FRR_A. | ||
0x51 | FRR_B_READ | Reads the fast response registers (FRR) starting with FRR_B. | ||
0x53 | FRR_C_READ | Reads the fast response registers (FRR) starting with FRR_C. | ||
0x57 | FRR_D_READ | Reads the fast response registers (FRR) starting with FRR_D. |
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RX_COMMANDS | |||
---|---|---|---|---|
Number | Name | Summary | Feature Available | |
0x16 | PACKET_INFO | Returns information about the length of the variable field in the last packet received, and (optionally) overrides field length. | ||
0x22 | GET_MODEM_STATUS | Returns the interrupt status of the Modem Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. | ||
0x32 | START_RX | Switches to RX state and starts reception of a packet. | ||
0x77 | READ_RX_FIFO | Reads data byte(s) from the RX FIFO. |
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ADVANCED_COMMANDS | |||
---|---|---|---|---|
Number | Name | Summary | Feature Available | |
0x14 | GET_ADC_READING | Performs conversions using the Auxiliary ADC and returns the results of those conversions. | ||
0x21 | GET_PH_STATUS | Returns the interrupt status of the Packet Handler Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. | ||
0x23 | GET_CHIP_STATUS | Returns the interrupt status of the Chip Interrupt Group (both STATUS and PENDING). Optionally, it may be used to clear latched (PENDING) interrupt events. |
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EZCONFIG_COMMANDS | |||
---|---|---|---|---|
Number | Name | Summary | Feature Available | |
0x19 | EZCONFIG_CHECK | Validates the EZConfig array was written correctly. | ||
0x66 | EZCONFIG_ARRAY_WRITE | Writes data byte(s) to the EZConfig array. |
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INT_CTL (0x01) | |||||
---|---|---|---|---|---|---|
Group | Number | Name | Default | Summary | Feature Available | |
0x01 | 0x00 | INT_CTL_ENABLE | 0x04 | This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. | ||
0x01 | 0x01 | INT_CTL_PH_ENABLE | 0x00 | Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. | ||
0x01 | 0x02 | INT_CTL_MODEM_ENABLE | 0x00 | Enable individual interrupt sources within the Modem Interrupt Group to generate a HW interrupt on the NIRQ output pin. | ||
0x01 | 0x03 | INT_CTL_CHIP_ENABLE | 0x04 | Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin. |
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FRR_CTL (0x02) | |||||
---|---|---|---|---|---|---|
Group | Number | Name | Default | Summary | Feature Available | |
0x02 | 0x00 | FRR_CTL_A_MODE | 0x01 | Fast Response Register A Configuration. | ||
0x02 | 0x01 | FRR_CTL_B_MODE | 0x02 | Fast Response Register B Configuration. | ||
0x02 | 0x02 | FRR_CTL_C_MODE | 0x09 | Fast Response Register C Configuration. | ||
0x02 | 0x03 | FRR_CTL_D_MODE | 0x00 | Fast Response Register D Configuration. |
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SYNC (0x11) | |||||
---|---|---|---|---|---|---|
Group | Number | Name | Default | Summary | Feature Available | |
0x11 | 0x00 | SYNC_CONFIG | 0x01 | Sync Word configuration bits. | ||
0x11 | 0x01 0x02 0x03 0x04 |
SYNC_BITS | 0x2d 0xd4 0x2d 0xd4 |
Sync word. |
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EZCONFIG (0x24) | |||||
---|---|---|---|---|---|---|
Group | Number | Name | Default | Summary | Feature Available | |
0x24 | 0x00 | EZCONFIG_MODULATION | 0x02 | Selects the type of modulation using the EZConfig feature. | ||
0x24 | 0x03 | EZCONFIG_XO_TUNE | 0x40 | Configure the internal capacitor frequency tuning bank for the crystal oscillator. |
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FREQ_CONTROL (0x40) | |||||
---|---|---|---|---|---|---|
Group | Number | Name | Default | Summary | Feature Available | |
0x40 | 0x00 | FREQ_CONTROL_INTE | 0x3c | Frac-N PLL Synthesizer integer divide number. | ||
0x40 | 0x01 0x02 0x03 |
FREQ_CONTROL_FRAC | 0x08 0x00 0x00 |
Frac-N PLL fraction number. | ||
0x40 | 0x04 0x05 |
FREQ_CONTROL_CHANNEL_STEP_SIZE | 0x00 0x00 |
EZ Frequency Programming channel step size. |
NOP Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x00 |
NOP Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS |
PART_INFO Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x01 |
PART_INFO Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | CHIPREV | CHIPREV | ||||||||
0x02 | PART | PART[15:8] | ||||||||
0x03 | PART[7:0] | |||||||||
0x04 | PBUILD | PBUILD | ||||||||
0x05 | ID | ID[15:8] | ||||||||
0x06 | ID[7:0] | |||||||||
0x07 | CUSTOMER | CUSTOMER | ||||||||
0x08 | ROMID | ROMID |
FUNC_INFO Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x10 |
FUNC_INFO Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | REVEXT | REVEXT | ||||||||
0x02 | REVBRANCH | REVBRANCH | ||||||||
0x03 | REVINT | REVINT | ||||||||
0x04 | PATCH | PATCH[15:8] | ||||||||
0x05 | PATCH[7:0] | |||||||||
0x06 | FUNC | FUNC |
SET_PROPERTY Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x11 | ||||||||
0x01 | GROUP | GROUP | ||||||||
0x02 | NUM_PROPS | NUM_PROPS | ||||||||
0x03 | START_PROP | START_PROP | ||||||||
0x04 | DATA[0] | DATA | ||||||||
... | ... | ... | ||||||||
0x0f | DATA[11] | DATA |
SET_PROPERTY Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS |
GET_PROPERTY Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x12 | ||||||||
0x01 | GROUP | GROUP | ||||||||
0x02 | NUM_PROPS | NUM_PROPS | ||||||||
0x03 | START_PROP | START_PROP |
GET_PROPERTY Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | DATA[0] | DATA | ||||||||
... | ... | ... | ||||||||
0x10 | DATA[15] | DATA |
GPIO_PIN_CFG Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x13 | ||||||||
0x01 | GPIO[0] | 0 | PULL_CTL | GPIO_MODE | ||||||
... | ... | ... | ... | ... | ||||||
0x04 | GPIO[3] | 0 | PULL_CTL | GPIO_MODE | ||||||
0x05 | NIRQ | 0 | PULL_CTL | NIRQ_MODE | ||||||
0x06 | SDO | 0 | PULL_CTL | SDO_MODE | ||||||
0x07 | GEN_CONFIG | 0 | DRV_STRENGTH | 0 | 0 | 0 | 0 | 0 |
GPIO_PIN_CFG Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | GPIO[0] | GPIO_STATE | X | GPIO_MODE | ||||||
... | ... | ... | ... | ... | ||||||
0x04 | GPIO[3] | GPIO_STATE | X | GPIO_MODE | ||||||
0x05 | NIRQ | NIRQ_STATE | X | NIRQ_MODE | ||||||
0x06 | SDO | SDO_STATE | X | SDO_MODE | ||||||
0x07 | GEN_CONFIG | X | DRV_STRENGTH | X | X | X | X | X |
Name | Value | Description | Feature Available |
---|---|---|---|
PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A |
PULL_EN | 1 | Enable pull-up resistor. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A |
RX_STATE | 33 | This output is set high while in RX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A |
RX_FIFO_FULL | 34 | This output is high while the number of bytes stored in the RX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A |
CCA_LATCH | 37 | This output goes high if the Current RSSI signal exceeds the threshold and remains high (i.e., is latched) even if the Current RSSI signal subsequently drops below the threshold value. The signal returns low upon detection of the Sync Word or upon exiting RX state. |
revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A |
PULL_EN | 1 | Enable pull-up resistor. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
NIRQ | 39 | Active low interrupt signal. | revBlA |
Name | Value | Description | Feature Available |
---|---|---|---|
PULL_DIS | 0 | Disable pull-up resistor (recommended setting if the pin is driven from an external source, other than an open-drain source). | revB1A |
PULL_EN | 1 | Enable pull-up resistor. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A |
MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A |
MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A |
LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
INACTIVE | 0 | Pin was read back as a 0. | revB1A |
ACTIVE | 1 | Pin was read back as a 1. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
IN_SLEEP | 28 | This output goes high when the chip is NOT in SLEEP state, and goes low when in SLEEP state. | revB1A |
RX_STATE | 33 | This output is set high while in RX state and is low otherwise. The TX_STATE and RX_STATE signals are typically used for control of peripheral circuits (e.g., a T/R Switch). | revB1A |
RX_FIFO_FULL | 34 | This output is high while the number of bytes stored in the RX FIFO exceeds the threshold value set by the ezconfig array, and is low otherwise. | revB1A |
CCA_LATCH | 37 | This output goes high if the Current RSSI signal exceeds the threshold and remains high (i.e., is latched) even if the Current RSSI signal subsequently drops below the threshold value. The signal returns low upon detection of the Sync Word or upon exiting RX state. |
revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
INACTIVE | 0 | Pin was read back as a 0. | revB1A |
ACTIVE | 1 | Pin was read back as a 1. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
NIRQ | 39 | Active low interrupt signal. | revBlA |
Name | Value | Description | Feature Available |
---|---|---|---|
INACTIVE | 0 | Pin was read back as a 0. | revB1A |
ACTIVE | 1 | Pin was read back as a 1. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DONOTHING | 0 | Behavior of this pin is not modified. | revB1A |
TRISTATE | 1 | Input and output drivers disabled. | revB1A |
DRIVE0 | 2 | Pin is configured as a CMOS output and driven low. | revB1A |
DRIVE1 | 3 | Pin is configured as a CMOS output and driven high. | revB1A |
INPUT | 4 | Pin is configured as a CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TXDATA input for TX Direct Mode). However, configuration of this pin as an input does NOT additionally select which internal circuit receives that input; that functionality is controlled by other properties, as appropriate. | revB1A |
SDO | 11 | Outputs the Serial Data Out (SDO) signal for the SPI bus. | revB1A |
POR | 12 | This output goes low during Power-On Reset and goes high upon completion of POR. | revB1A |
RX_DATA_CLK | 17 | Outputs the RX Data CLK signal. This signal is nominally a square wave that is synchronized to the received data rate, and is typically used to latch the RX Data signal into the host MCU. | revB1A |
EN_LNA | 18 | This output goes low when the internal LNA is enabled. | revB1A |
RX_DATA | 20 | Outputs the demodulated RX Data stream, after synchronization and re-timing by the local RX Data Clock. | revB1A |
RX_RAW_DATA | 21 | Outputs the demodulated RX Raw Data stream, prior to synchronization and re-timing by the local RX Data Clock. | revB1A |
VALID_PREAMBLE | 24 | This output goes high when a valid preamble is detected, and returns low after the packet is received or Sync Word timeout occurs. | revB1A |
INVALID_PREAMBLE | 25 | Output low normally, pulses output high when the preamble is not detected within a period time after the demodulator is enabled. | revB1A |
SYNC_WORD_DETECT | 26 | This output goes high when a Sync Word is detected, and returns low after the packet is received. | revB1A |
CCA | 27 | Clear Channel Assessment. This output goes high when the Current RSSI signal exceeds the threshold, and is low when the Current RSSI is below threshold. This is a real-time (non-latched) signal. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
HIGH | 0 | GPIOs configured as outputs will have the highest drive strength. | revB1A |
MED_HIGH | 1 | GPIOs configured as outputs will have a medium drive strength. | revB1A |
MED_LOW | 2 | GPIOs configured as outputs will have a medium drive strength. | revB1A |
LOW | 3 | GPIOs configured as outputs will have the lowest drive strength. | revB1A |
FIFO_INFO Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x15 | ||||||||
0x01 | FIFO | 0 | 0 | 0 | 0 | 0 | 0 | RX | 0 |
FIFO_INFO Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | RX_FIFO_COUNT | RX_FIFO_COUNT |
Name | Value | Description | Feature Available |
---|---|---|---|
FALSE | 0 | Do not reset the RX data FIFO. | revB1A |
TRUE | 1 | Reset the RX data FIFO. | revB1A |
GET_INT_STATUS Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x20 | ||||||||
0x01 | PH_CLR_PEND | 0 | 0 | 0 | PACKET_RX_PEND_CLR | CRC_ERROR_PEND_CLR | 0 | 0 | RX_FIFO_ALMOST_FULL_PEND_CLR | |
0x02 | MODEM_CLR_PEND | 0 | 0 | INVALID_SYNC_PEND_CLR | 0 | RSSI_PEND_CLR | INVALID_PREAMBLE_PEND_CLR | PREAMBLE_DETECT_PEND_CLR | SYNC_DETECT_PEND_CLR | |
0x03 | CHIP_CLR_PEND | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | 0 | 0 |
GET_INT_STATUS Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | INT_PEND | X | X | X | X | X | CHIP_INT_PEND | MODEM_INT_PEND | PH_INT_PEND | |
0x02 | INT_STATUS | X | X | X | X | X | CHIP_INT_STATUS | MODEM_INT_STATUS | PH_INT_STATUS | |
0x03 | PH_PEND | X | X | X | PACKET_RX_PEND | CRC_ERROR_PEND | X | X | RX_FIFO_ALMOST_FULL_PEND | |
0x04 | PH_STATUS | X | X | X | PACKET_RX | CRC_ERROR | X | X | RX_FIFO_ALMOST_FULL | |
0x05 | MODEM_PEND | X | X | INVALID_SYNC_PEND | X | RSSI_PEND | INVALID_PREAMBLE_PEND | PREAMBLE_DETECT_PEND | SYNC_DETECT_PEND | |
0x06 | MODEM_STATUS | X | X | INVALID_SYNC | X | RSSI | INVALID_PREAMBLE | PREAMBLE_DETECT | SYNC_DETECT | |
0x07 | CHIP_PEND | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | X | X | |
0x08 | CHIP_STATUS | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | X | X |
REQUEST_DEVICE_STATE Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x33 |
REQUEST_DEVICE_STATE Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | CURR_STATE | X | X | X | X | MAIN_STATE | ||||
0x02 | CURRENT_CHANNEL | CURRENT_CHANNEL |
Name | Value | Description | Feature Available |
---|---|---|---|
SLEEP | 1 | (Not Applicable) | revB1A |
SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A |
READY | 3 | READY state. | revB1A |
READY2 | 4 | Another enumeration for READY state. | revB1A |
RX_TUNE | 6 | RX_TUNE state. | revB1A |
RX | 8 | RX state. | revB1A |
CHANGE_STATE Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x34 | ||||||||
0x01 | NEXT_STATE1 | 0 | 0 | 0 | 0 | NEW_STATE |
CHANGE_STATE Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS |
Name | Value | Description | Feature Available |
---|---|---|---|
NOCHANGE | 0 | No change, remain in current state. | revB1A |
SLEEP | 1 | SLEEP state. | revB1A |
SPI_ACTIVE | 2 | SPI_ACTIVE state. | revB1A |
READY | 3 | READY state. | revB1A |
RX_TUNE | 6 | RX_TUNE state. | revB1A |
RX | 8 | RX state. | revB1A |
READ_CMD_BUFF Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x44 |
READ_CMD_BUFF Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | BYTE[0] | CMD_BUFF | ||||||||
... | ... | ... | ||||||||
0x10 | BYTE[15] | CMD_BUFF |
FRR_A_READ Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x50 |
FRR_A_READ Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | FRR_A_VALUE | FRR_A_VALUE | ||||||||
0x01 | FRR_B_VALUE | FRR_B_VALUE | ||||||||
0x02 | FRR_C_VALUE | FRR_C_VALUE | ||||||||
0x03 | FRR_D_VALUE | FRR_D_VALUE |
FRR_B_READ Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x51 |
FRR_B_READ Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | FRR_B_VALUE | FRR_B_VALUE | ||||||||
0x01 | FRR_C_VALUE | FRR_C_VALUE | ||||||||
0x02 | FRR_D_VALUE | FRR_D_VALUE | ||||||||
0x03 | FRR_A_VALUE | FRR_A_VALUE |
FRR_C_READ Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x53 |
FRR_C_READ Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | FRR_C_VALUE | FRR_C_VALUE | ||||||||
0x01 | FRR_D_VALUE | FRR_D_VALUE | ||||||||
0x02 | FRR_A_VALUE | FRR_A_VALUE | ||||||||
0x03 | FRR_B_VALUE | FRR_B_VALUE |
FRR_D_READ Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x57 |
FRR_D_READ Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | FRR_D_VALUE | FRR_D_VALUE | ||||||||
0x01 | FRR_A_VALUE | FRR_A_VALUE | ||||||||
0x02 | FRR_B_VALUE | FRR_B_VALUE | ||||||||
0x03 | FRR_C_VALUE | FRR_C_VALUE |
PACKET_INFO Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x16 | ||||||||
0x01 | FIELD_NUMBER | 0 | 0 | 0 | FIELD_NUM | |||||
0x02 | LEN | LEN[15:8] | ||||||||
0x03 | LEN[7:0] | |||||||||
0x04 | LEN_DIFF | LEN_DIFF[15:8] | ||||||||
0x05 | LEN_DIFF[7:0] |
PACKET_INFO Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | LENGTH | LENGTH[15:8] | ||||||||
0x02 | LENGTH[7:0] |
Name | Value | Description | Feature Available |
---|---|---|---|
ENUM_0 | 0 | Do not override the length of any data fields. | |
ENUM_1 | 1 | Override the programmed value of PKT_FIELD_1_LENGTH, or the value of RX_LEN in the START_RX command. | |
ENUM_2 | 2 | Override the programmed value of PKT_FIELD_2_LENGTH. | |
ENUM_3 | 4 | Override the programmed value of PKT_FIELD_3_LENGTH. | |
ENUM_4 | 8 | Override the programmed value of PKT_FIELD_4_LENGTH. | |
ENUM_5 | 16 | Override the programmed value of PKT_FIELD_5_LENGTH. |
GET_MODEM_STATUS Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x22 | ||||||||
0x01 | MODEM_CLR_PEND | 0 | 0 | INVALID_SYNC_PEND_CLR | 0 | RSSI_PEND_CLR | INVALID_PREAMBLE_PEND_CLR | PREAMBLE_DETECT_PEND_CLR | SYNC_DETECT_PEND_CLR |
GET_MODEM_STATUS Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | MODEM_PEND | X | X | INVALID_SYNC_PEND | X | RSSI_PEND | INVALID_PREAMBLE_PEND | PREAMBLE_DETECT_PEND | SYNC_DETECT_PEND | |
0x02 | MODEM_STATUS | X | X | INVALID_SYNC | X | RSSI | INVALID_PREAMBLE | PREAMBLE_DETECT | SYNC_DETECT | |
0x03 | CURR_RSSI | CURR_RSSI | ||||||||
0x04 | LATCH_RSSI | LATCH_RSSI | ||||||||
0x05 | RESERVED0 | X | X | X | X | X | X | X | X | |
0x06 | RESERVED1 | X | X | X | X | X | X | X | X | |
0x07 | AFC_FREQ_OFFSET | AFC_FREQ_OFFSET[15:8] | ||||||||
0x08 | AFC_FREQ_OFFSET[7:0] |
START_RX Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x32 | ||||||||
0x01 | CHANNEL | CHANNEL | ||||||||
0x02 | RESERVED0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
0x03 | RX_LEN | 0 | 0 | 0 | RX_LEN[12:8] | |||||
0x04 | RX_LEN[7:0] | |||||||||
0x05 | NEXT_STATE1 | 0 | 0 | 0 | 0 | RXTIMEOUT_STATE | ||||
0x06 | NEXT_STATE2 | 0 | 0 | 0 | 0 | RXVALID_STATE | ||||
0x07 | NEXT_STATE3 | 0 | 0 | 0 | 0 | RXINVALID_STATE |
START_RX Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS |
Name | Value | Description | Feature Available |
---|---|---|---|
NOCHANGE | 0 | Remain in RX state if RXTIMEOUT occurs. | |
SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operation of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | |
SPI_ACTIVE | 2 | SPI ACTIVE state. | |
READY | 3 | READY state. | |
READY2 | 4 | Another enumeration for READY state. | |
RX_TUNE | 6 | RX_TUNE state. | |
RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). |
Name | Value | Description | Feature Available |
---|---|---|---|
REMAIN | 0 | Remain in RX state (but do not re-arm to acquire another packet). | revB1A |
SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A |
SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A |
READY | 3 | READY state. | revB1A |
READY2 | 4 | Another enumeration for READY state. | revB1A |
RX_TUNE | 6 | RX_TUNE state. | revB1A |
RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
REMAIN | 0 | Remain in RX state (but do not re-arm to acquire another packet). | revB1A |
SLEEP | 1 | SLEEP or STANDBY state, according to the mode of operotion of the 32K R-C Osc selected by GLOBAL_CLK_CFG:CLK_32K_SEL. | revB1A |
SPI_ACTIVE | 2 | SPI ACTIVE state. | revB1A |
READY | 3 | READY state. | revB1A |
READY2 | 4 | Another enumeration for READY state. | revB1A |
RX_TUNE | 6 | RX_TUNE state. | revB1A |
RX | 8 | RX state (briefly exit and re-enter RX state to re-arm for acquisition of another packet). | revB1A |
READ_RX_FIFO Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x77 |
READ_RX_FIFO Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | DATA[0] | DATA | ||||||||
... | ... | ... | ||||||||
M | DATA[N] | DATA |
GET_ADC_READING Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x14 | ||||||||
0x01 | ADC_EN | 0 | 0 | 0 | 0 | BATTERY_VOLTAGE_EN | ADC_GPIO_EN | ADC_GPIO_PIN | ||
0x02 | ADC_CFG | UDTIME | GPIO_ATT |
GET_ADC_READING Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | GPIO_ADC | X | X | X | X | X | GPIO_ADC[10:8] | |||
0x02 | GPIO_ADC[7:0] | |||||||||
0x03 | BATTERY_ADC | X | X | X | X | X | BATTERY_ADC[10:8] | |||
0x04 | BATTERY_ADC[7:0] |
Name | Value | Description | Feature Available |
---|---|---|---|
ENUM_0 | 0 | Do not perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will always be 0x000. | revB1A |
ENUM_1 | 1 | Perform ADC conversion of the battery voltage. The reply value in BATTERY_ADC will be VBAT(V) = 3*BATTERY_ADC/1280. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
ENUM_0 | 0 | Do not perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will always be 0x000. | revB1A |
ENUM_1 | 1 | Perform ADC conversion of the voltage applied to the selected GPIO pin. The reply value in GPIO_ADC will be VGPIO(V) = GPIO_ADC/GPIO_ADC_DIV, where GPIO_ADC_DIV is an attenuation factor defined by the selection of the GPIO_ATT parameter. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
ENUM_0 | 0 | The voltage on GPIO0 will be converted by the ADC. | revB1A |
ENUM_1 | 1 | The voltage on GPIO1 will be converted by the ADC. | revB1A |
ENUM_2 | 2 | The voltage on GPIO2 will be converted by the ADC. | revB1A |
ENUM_3 | 3 | The voltage on GPIO3 will be converted by the ADC. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
0P8 | 0 | ADC measurement range is 0 to 0.8 V. GPIO_ADC_DIV = 2560. | revB1A |
1P6 | 4 | ADC measurement range is 0 to 1.6 V. GPIO_ADC_DIV = 1280. | revB1A |
3P2 | 5 | ADC measurement range is 0 to 3.2 V. GPIO_ADC_DIV = 640. | revB1A |
2P4 | 8 | ADC measurement range is 0 to 2.4 V. GPIO_ADC_DIV = 853.33. | revB1A |
3P6 | 9 | ADC measurement range is 0 to 3.6 V. GPIO_ADC_DIV = 426.66. | revB1A |
GET_PH_STATUS Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x21 | ||||||||
0x01 | PH_CLR_PEND | 0 | 0 | 0 | PACKET_RX_PEND_CLR | CRC_ERROR_PEND_CLR | 0 | 0 | RX_FIFO_ALMOST_FULL_PEND_CLR |
GET_PH_STATUS Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | PH_PEND | X | X | X | PACKET_RX_PEND | CRC_ERROR_PEND | X | X | RX_FIFO_ALMOST_FULL_PEND | |
0x02 | PH_STATUS | X | X | X | PACKET_RX | CRC_ERROR | X | X | RX_FIFO_ALMOST_FULL |
GET_CHIP_STATUS Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x23 | ||||||||
0x01 | CHIP_CLR_PEND | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR | STATE_CHANGE_PEND_CLR | CMD_ERROR_PEND_CLR | CHIP_READY_PEND_CLR | 0 | 0 |
GET_CHIP_STATUS Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | CHIP_PEND | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND | STATE_CHANGE_PEND | CMD_ERROR_PEND | CHIP_READY_PEND | X | X | |
0x02 | CHIP_STATUS | X | X | FIFO_UNDERFLOW_OVERFLOW_ERROR | STATE_CHANGE | CMD_ERROR | CHIP_READY | X | X | |
0x03 | CMD_ERR_STATUS | CMD_ERR_STATUS | ||||||||
0x04 | CMD_ERR_CMD_ID | CMD_ERR_CMD_ID |
Name | Value | Description | Feature Available |
---|---|---|---|
CMD_ERROR_NONE | 0 | No error. | |
CMD_ERROR_BAD_COMMAND | 16 | Bad command issued. | |
CMD_ERROR_BAD_ARG | 17 | Argment(s) in issued command were invalid. | |
CMD_ERROR_COMMAND_BUSY | 18 | Command was issued before previous command was completed. | |
CMD_ERROR_BAD_BOOTMODE | 49 | Invalid bootmode supplied. | |
CMD_ERROR_BAD_PROPERTY | 64 | Bad Property ID was provided. |
EZCONFIG_CHECK Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x19 | ||||||||
0x01 | CHECKSUM | CHECKSUM[15:8] | ||||||||
0x02 | CHECKSUM[7:0] |
EZCONFIG_CHECK Reply Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CTS | CTS | ||||||||
0x01 | RESULT | RESULT |
Name | Value | Description | Feature Available |
---|---|---|---|
VALID | 0 | EZConfig array is valid. The chip is now in normal operating state. | |
BAD_CHECKSUM | 1 | EZConfig array is invalid. EZConfig state re-started. | |
INVALID_STATE | 2 | The chip was not in the EZConfig state at the time the EZCONFIG_CHECK command was issued. |
EZCONFIG_ARRAY_WRITE Argument Stream | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|
Index | Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | CMD | 0x66 | ||||||||
0x01 | DATA[0] | DATA | ||||||||
... | ... | ... | ||||||||
M | DATA[N] | DATA |
INT_CTL_ENABLE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | 0 | 0 | 0 | 0 | 0 | CHIP_INT_STATUS_EN | MODEM_INT_STATUS_EN | PH_INT_STATUS_EN | |
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disable pending interrupts in the Chip Status group from asserting nNIRQ. | revB1A |
ENABLED | 1 | Enable pending interrupts in the Chip Status group to assert nNIRQ. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disable pending interrupts in rx mode group from asserting nNIRQ. | |
ENABLED | 1 | Enable pending interrupts in rx mode group to assert nNIRQ. |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disable pending interrupts in tx mode group from asserting nNIRQ. | |
ENABLED | 1 | Enable pending interrupts in tx mode group to assert nNIRQ. |
INT_CTL_PH_ENABLE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x01 | 0 | 0 | 0 | PACKET_RX_EN | CRC_ERROR_EN | 0 | 0 | RX_FIFO_ALMOST_FULL_EN | |
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 |
INT_CTL_MODEM_ENABLE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x02 | RSSI_LATCH_EN | 0 | INVALID_SYNC_EN | 0 | RSSI_EN | INVALID_PREAMBLE_EN | PREAMBLE_DETECT_EN | SYNC_DETECT_EN | |
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 |
INT_CTL_CHIP_ENABLE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x03 | 0 | 0 | FIFO_UNDERFLOW_OVERFLOW_ERROR_EN | STATE_CHANGE_EN | CMD_ERROR_EN | CHIP_READY_EN | 0 | 0 | |
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 |
FRR_CTL_A_MODE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | FRR_A_MODE | ||||||||
Default | |||||||||
0x1 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disabled. Will always read back 0. | revB1A |
INT_STATUS | 1 | Global status. | revB1A |
INT_PEND | 2 | Global interrupt pending. | revB1A |
INT_PH_STATUS | 3 | Packet Handler status. | revB1A |
INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A |
INT_MODEM_STATUS | 5 | Modem status. | revB1A |
INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A |
INT_CHIP_STATUS | 7 | Chip status. | revB1A |
INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A |
CURRENT_STATE | 9 | Current state. | revB1A |
LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A |
FRR_CTL_B_MODE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x01 | FRR_B_MODE | ||||||||
Default | |||||||||
0x2 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disabled. Will always read back 0. | revB1A |
INT_STATUS | 1 | Global status. | revB1A |
INT_PEND | 2 | Global interrupt pending. | revB1A |
INT_PH_STATUS | 3 | Packet Handler status. | revB1A |
INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A |
INT_MODEM_STATUS | 5 | Modem status. | revB1A |
INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A |
INT_CHIP_STATUS | 7 | Chip status. | revB1A |
INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A |
CURRENT_STATE | 9 | Current state. | revB1A |
LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A |
FRR_CTL_C_MODE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x02 | FRR_C_MODE | ||||||||
Default | |||||||||
0x9 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disabled. Will always read back 0. | revB1A |
INT_STATUS | 1 | Global status. | revB1A |
INT_PEND | 2 | Global interrupt pending. | revB1A |
INT_PH_STATUS | 3 | Packet Handler status. | revB1A |
INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A |
INT_MODEM_STATUS | 5 | Modem status. | revB1A |
INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A |
INT_CHIP_STATUS | 7 | Chip status. | revB1A |
INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A |
CURRENT_STATE | 9 | Current state. | revB1A |
LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A |
FRR_CTL_D_MODE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x03 | FRR_D_MODE | ||||||||
Default | |||||||||
0x0 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Disabled. Will always read back 0. | revB1A |
INT_STATUS | 1 | Global status. | revB1A |
INT_PEND | 2 | Global interrupt pending. | revB1A |
INT_PH_STATUS | 3 | Packet Handler status. | revB1A |
INT_PH_PEND | 4 | Packet Handler interrupt pending. | revB1A |
INT_MODEM_STATUS | 5 | Modem status. | revB1A |
INT_MODEM_PEND | 6 | Modem interrupt pending. | revB1A |
INT_CHIP_STATUS | 7 | Chip status. | revB1A |
INT_CHIP_PEND | 8 | Chip status interrupt pending. | revB1A |
CURRENT_STATE | 9 | Current state. | revB1A |
LATCHED_RSSI | 10 | Latched RSSI value as defined in MODEM_RSSI_CONTROL:LATCH. | revB1A |
SYNC_CONFIG | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | 0 | RX_ERRORS | 0 | MANCH | LENGTH | ||||
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x1 |
Name | Value | Description | Feature Available |
---|---|---|---|
DISABLED | 0 | Sync word is not manchester encoded. | revB1A |
ENABLED | 1 | Sync word is manchester encoded. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
LEN_1_BYTES | 0 | Sync Word is 1-byte (8 bits) in length. Sync Word byte 3 [31:24] is used, with its value defined in the SYNC_BITS property. | revB1A |
LEN_2_BYTES | 1 | Sync Word is 2-bytes (16 bits) in length. Sync Word bytes 3 and 2 [31:16] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A |
LEN_3_BYTES | 2 | Sync Word is 3-bytes (24 bits) in length. Sync Word bytes 3, 2, and 1 [31:8] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A |
LEN_4_BYTES | 3 | Sync Word is 4-bytes (32 bits) in length. Sync Word bytes 3, 2, 1, and 0 [31:0] are used (in descending order), with their values defined in the SYNC_BITS property. | revB1A |
SYNC_BITS | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x01 | BITS[31:24] | ||||||||
0x02 | BITS[23:16] | ||||||||
0x03 | BITS[15:8] | ||||||||
0x04 | BITS[7:0] | ||||||||
Defaults | |||||||||
0x01 | 0x2d | ||||||||
0x02 | 0xd4 | ||||||||
0x03 | 0x2d | ||||||||
0x04 | 0xd4 |
EZCONFIG_MODULATION | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | 0 | 00 | MOD_SOURCE | 0 | MOD_TYPE | ||||
Default | |||||||||
0x0 | 0x0 | 0x0 | 0x0 | 0x2 |
Name | Value | Description | Feature Available |
---|---|---|---|
PACKET | 0 | The modulation is sourced from the TX FIFO in the packet handler. | revB1A |
DIRECT | 1 | The modulation is sourced in real-time (i.e., TX Direct Mode) from a GPIO pin, as selected by the TX_DIRECT_MODE_GPIO field. | revB1A |
PSEUDO | 2 | The modulation is sourced from the internal pseudo-random generator. | revB1A |
Name | Value | Description | Feature Available |
---|---|---|---|
OOK | 1 | OOK. | revB1A |
2FSK | 2 | 2FSK. | revB1A |
2GFSK | 3 | 2GFSK. | revB1A |
EZCONFIG_XO_TUNE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x03 | 0 | TUNE_VALUE | |||||||
Default | |||||||||
0x0 | 0x40 |
Name | Value | Description | Feature Available |
---|---|---|---|
FASTEST_FREQUENCY | 0 | Lowest capacitance (i.e., highest oscillation frequency). | revB1A |
SLOWEST_FREQUENCY | 127 | Highest capacitance (i.e., lowest oscillation frequency). | revB1A |
FREQ_CONTROL_INTE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x00 | 0 | INTE | |||||||
Default | |||||||||
0x0 | 0x3c |
FREQ_CONTROL_FRAC | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x01 | 0 | 0 | 0 | 0 | FRAC[19:16] | ||||
0x02 | FRAC[15:8] | ||||||||
0x03 | FRAC[7:0] | ||||||||
Defaults | |||||||||
0x01 | 0x0 | 0x0 | 0x0 | 0x0 | 0x8 | ||||
0x02 | 0x0 | ||||||||
0x03 | 0x0 |
FREQ_CONTROL_CHANNEL_STEP_SIZE | |||||||||
---|---|---|---|---|---|---|---|---|---|
Index | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
0x04 | CHANNEL_STEP_SIZE[15:8] | ||||||||
0x05 | CHANNEL_STEP_SIZE[7:0] | ||||||||
Defaults | |||||||||
0x04 | 0x0 | ||||||||
0x05 | 0x0 |