EFM32™ Jade Gecko 32-bit Microcontroller

Our Jade Gecko 32-bit microcontroller (MCU) family boasts ultra-low active power modes and short wake-up time from energy-saving modes, making it well-suited for battery-powered applications or other systems requiring high performance and low-energy consumption.  

The EFM32™ Jade Gecko features a powerful 32-bit ARM® Cortex®-M3 and offers a wide selection of peripherals, including a unique cryptographic hardware engine supporting AES, ECC, and SHA. 

Sleep current with RTC as low as
2.1 μA
Active current as low as
64 μA/MHz

Jade Gecko Common Specs

  • ARM Cortex-M4 CPU platform
  • 40 MHz
  • Up to 1024 Flash
  • Up to 256 kB RAM
  • 64 μA/MHz in Active Mode (EM0)
  • 2.1 μA sleep with RTC and RAM retention
  • Autonomous peripherals in sleep
  • DMA and peripheral reflex system
  • LESENSE
  • USART, I²C, and SPI
  • Up to 65 General Purpose I/O Pins
  • -40 °C to +85 °C TJ temperature grade
  • 1.8 V to 3.8 V single power supply
  • Packages:
    • 32-pin QFN (5 mm x 5 mm)
    • 48-pin QFN (7 mm x 7 mm)
    • 125-pin BGA (7 mm x 7 mm)
Status
Find the Right Jade Gecko Device Select Columns
Select Columns
Part Number MHz Flash RAM Dig I/O Pins 5 Volt Tolerant ADC 1 DAC USB Cap Sense LCD Temp Sensor Timers (16-bit) UART USART SPI I2C I2S EMIF RTC Comparators Vdd (min) Vdd (max) Package Type Package Size (mm) Internal Osc. Debug Interface Cryptography CRYOTIMER LETIMER Op-Amp sl:pcntchannels Timers (32-bit) DC-DC LESENSE Temperature Range (ºC)
40 1024 256 65 12-bit, 54-ch., 1 Msps 2x 12-bit, 54-ch., 500 ksps 2 0 4 4 2 2 0 2 1.8 3.8 BGA125 7x7 ±2% JTAG; SW; ETM AES-128 AES-256 ECC SHA-1 SHA-2 TRNG SMU 1 1 3 3 2 -40 85
40 1024 256 33 12-bit, 33-ch., 1 Msps 2x 12-bit, 33-ch., 500 ksps 2 0 4 4 2 2 0 2 1.8 3.8 QFN48 7x7 ±2% JTAG; SW; ETM AES-128 AES-256 ECC SHA-1 SHA-2 TRNG SMU 1 1 3 3 2 -40 85
40 1024 256 65 12-bit, 54-ch., 1 Msps 2x 12-bit, 54-ch., 500 ksps 2 0 4 4 2 2 0 2 1.8 3.8 BGA125 7x7 ±2% JTAG; SW; ETM AES-128 AES-256 ECC SHA-1 SHA-2 TRNG SMU 1 1 3 3 2 -40 125
40 1024 256 33 12-bit, 33-ch., 1 Msps 2x 12-bit, 33-ch., 500 ksps 2 0 4 4 2 2 0 2 1.8 3.8 QFN48 7x7 ±2% JTAG; SW; ETM AES-128 AES-256 ECC SHA-1 SHA-2 TRNG SMU 1 1 3 3 2 -40 125
40 128 32 24 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 256 32 24 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 256 32 24 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 125
40 128 32 20 12-bit, 20-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 128 32 32 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN48 7x7 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 256 32 20 12-bit, 20-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 256 32 32 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN48 7x7 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 85
40 256 32 20 12-bit, 20-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN32 5x5 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 125
40 256 32 32 12-bit, 24-ch., 1 Msps 2 0 2 2 1 1 0 2 1.85 3.8 QFN48 7x7 ±2% JTAG; SW AES-128 AES-256 ECC SHA-1 SHA-2 1 1 0 1 0 -40 125

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