SiM3L1xx Low Power MCUs

Silicon Labs’ ultra-low-power Precision32™ SiM3L1xx 32-bit microcontrollers (MCUs) feature significant peripheral and architectural innovations, including an integrated dc-dc converter that helps save power in active mode as well as a redesigned LCD controller that can reduce the power consumed by the LCD display.

Autonomous peripherals off-load the 50 MHz ARM® Cortex®-M3 CPU and further decrease processing time and power. Full RAM and state retention enable instantaneous code execution after waking up from sleep. Flash memory sizes range from 32 to 256 kB, and the MCUs come in packages as small as 5.5 mm x 5.5 mm. Enhanced Precision32 tools can simplify the development process by estimating power consumption and providing configuration guidance to achieve the lowest power.

SiM3L1xx Common Specs

  • Up to 256 kB flash
  • Up to 32 kB RAM
  • Up to 62 GPIOs
  • 50 MHz Cortex-M3 core
  • Integrated dc-dc converter
  • Variety of wake sources
  • 128 or 160 segment LCD controller
  • Sensor interface
  • Hardware AES, CRC, encode/decode
  • Enhanced DMA with DTM
  • 10-bit 1 Msps or 12-bit 250 ksps ADC
  • Current mode DAC
  • 2 x SPI, UART and I²C
  • Analog comparators
  • Enhanced PCA, timers
  • Voltage reference and temperature sensor
  • Available in 40, 64, 80-pin packages
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Part Number MHz Flash RAM Dig I/O Pins 5 Volt Tolerant ADC 1 DAC USB Cap Sense LCD Temp Sensor Timers (16-bit) AES-128 AES-256 ECC SHA-1 SHA-2 RSA-2048 UART USART SPI I2C I2S EMIF RTC Comparators Vdd (min) Vdd (max) Package Type Package Size (mm) Internal Osc. Debug Interface
50 32 8 28 12-bit, 20-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN40 6x6 ±2% SW
50 32 8 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN64 9x9 ±2% ETM; SW
50 32 8 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP64 10x10 ±2% ETM; SW
50 64 16 28 12-bit, 20-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN40 6x6 ±2% SW
50 64 16 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN64 9x9 ±2% ETM; SW
50 64 16 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP64 10x10 ±2% ETM; SW
50 128 32 28 12-bit, 20-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN40 6x6 ±2% SW
50 128 32 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN64 9x9 ±2% ETM; SW
50 128 32 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP64 10x10 ±2% ETM; SW
50 128 32 62 12-bit, 24-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP80 12x12 ±2% ETM; JTAG; SW
50 256 32 28 12-bit, 20-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN40 6x6 ±2% SW
50 256 32 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 QFN64 9x9 ±2% ETM; SW
50 256 32 51 12-bit, 23-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP64 10x10 ±2% ETM; SW
50 256 32 62 12-bit, 24-ch., 250 ksps 3 2 1 2 1 0 0 2 1.8 3.8 TQFP80 12x12 ±2% ETM; JTAG; SW

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