Silicon Labs' "Triple-Play" in 56G SerDes Timing Solutions
Silicon Labs is the leader in reliable, high-performance Timing solutions that solve communications designers’ most challenging problems. Leading manufacturers of switch SoCs, PHYs, FPGAs and ASICs, are migrating to 56G PAM-4 SerDes technology to support higher bandwidth 100G+ Ethernet and optical networking designs. To meet the stringent jitter requirements of 56G SerDes reference clocks, hardware developers need clocks with sub-100fs (typical) RMS phase jitter specifications to give them the greatest design margin. These designs typically need a mix of other frequencies for CPU and system clocks. Silicon Labs is the first timing supplier to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device.
Silicon Labs is the only timing supplier to offer a “triple-play” selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and crystal oscillators (XOs) for 100/200/400/600G designs that satisfy sub-100fs reference clock jitter requirements with margin.