Si53308-B-GM  Universal 2 : 6 Low Jitter Clock Buffer/Level Translator

Frequency Max (MHz)

The Si53308-B-GM is a universal 2 : 6 low jitter clock buffer/level translator with pin-selectable output clock signal format and divider selection. The Si53308-B-GM features a glitchless switching mux, making it ideal for redundant clocking applications. The Si53308-B-GM utilizes Silicon Laboratories' advanced CMOS technology to fanout 6 from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53308-B-GM features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.

Similar Devices: SI53308-B-GM

View Datasheet for all specifications View Datasheet for all specifications View Datasheet for all specifications
Specifications Summary

Inputs: 2

Outputs: 6

Frequency Min (MHz): 1

Frequency Max (MHz): 725

Additive Jitter (ps): 0.05

Zero Delay Mode: No

Package Type: QFN32

Package Size (mm): 5x5

Development Tools Type
Si53301/4 Clock Buffer Development Kit Development Kits
Title Version Resource Type
Si53308 Dual 1:3 Low-Jitter Universal Buffer/Level Translator 1.0 Data Sheets
PCN #1511251: PCN General Si533xx ShipMedia Product Change Notifications (PCN)
PB #1603041: Si53308rev 1.0 New release Product Change Notifications (PCN)
Si53308-B-GM IBIS Model 3.1 Software
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
EOL #1403114: Global Foundries (GFSG) 35um and Last Time Buy (LTB) Product Change Notifications (PCN)
PB #1410022 Si53302 Si53301 v1.1 datasheet Product Change Notifications (PCN)
EOL #1309161: SL38007 Clock Generator EOL Product Change Notifications (PCN)
PCN1308282 SL15300EZC Double Ground Wire UTACTH Product Change Notifications (PCN)
PCN #1309162: SL38X 20QFN 4x4 Silicon Clocks Assembly Test Site Change UTACTH Product Change Notifications (PCN)
AN766: Understanding and Optimizing Clock Buffer's Additive Jitter Performance 0.1 Application Notes
SI53308 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI53312 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
時脈樹設計原則 1.0 White Papers
时钟树设计原则 1.0 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Contact Sales Contact Sales
Close
Loading Results