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SL23EP09 CMOS Zero Delay Clock Buffer

Note: This device is not recommended for new designs (NRND).

The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce 9 clock outputs from 1 reference input(s) for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin.

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Specifications Summary

Inputs: 1

Outputs: 9

Frequency Min (MHz): 10

Frequency Max (MHz): 220

Additive Jitter (ps):

Zero Delay Mode: Yes

Package Type: SOIC16; TSSOP16

Title Version Resource Type
SL23EP09 Data Sheet 2.0 Data Sheets
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SI53308 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI53312 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
時脈樹設計原則 1.0 White Papers
时钟树设计原则 1.0 White Papers
171117179-Assembly-Site-Addition-UTL3 Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
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Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
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Timing Product Selector Guide Brochures
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